Mitsubishi Electric WS0-CPU0 Operating Manual page 259

Figure 239:
Sequence/timing diagram,
when the PSDI input is Low,
Upstroke muting is inactive
and Restart interlock is set
to "Always"
Figure 240:
Sequence/timing diagram
when the PSDI input is Low,
Max. Up-Stroke muting time
> 0 and Restart interlock is
set to "Deactivation on
upstroke (only for PSDI)"
Logic programming – Function blocks
If Restart interlock has been set to Always and upstroke muting is active, the
Enable output remains High until the Top input becomes High, thus indicating that the
press cycle has been completed. In this case, a complete restart sequence is required.
If Restart interlock has been set to Deactivation on upstroke (only for PSDI) and
the Upstroke input is High, the Enable output remains High until Top becomes High,
thus indicating that the press cycle has been completed. In this case, a cycle start
sequence is required.
If the PSDI input changes after the Max. Up-Stroke muting time has elapsed from
High to Low and back to High, the Enable output also changes from High to Low
and back to High. The setting for this parameter does not have any effect when the
Restart and Upstroke input signals remain unconnected.
Output signals of the function block
Restart required output
The Restart required output is High when a valid restart sequence is expected at the
Restart input.
PSDI required output
The PSDI required output is High when a break is expected at the PSDI input.
Chapter 9
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