Mitsubishi Electric WS0-CPU0 Operating Manual page 249

Figure 229:
Sequence/timing diagram
for the Press single stroke
function block when
Start/Release is configured
in stepping mode
Figure 230:
Sequence/timing diagram
for the Press single stroke
function block when
Start/Release is configured
in start only mode
Figure 231:
Sequence/timing diagram
for the Press single stroke
function block with upstroke
muting of Start/Release and
Release 3 (safety)
Logic programming – Function blocks
Restart input
If the Restart interlock parameter has been set to Without, a Restart signal is not
required in order to restart the press after any kind of stop. The Restart interlock
parameter can also be set to the following values:
 When Release 1 or Release 3 or Start/Release is Low
 When Release 1 or Release 3 is Low or Top changes to High
 Always
 When Release 1 or Release 3 is Low
This parameter determines when a Restart signal is expected as input signal for the
function block.
If the Enable output changes to Low because of the above-mentioned settings of the
configuration parameters for the Restart interlock, the Enable output can only be reset
after a valid restart sequence with a Low-High-Low transition (minimum 100 ms or 350
ms; shorter pulses and pulses longer than 30 s will be ignored) has been carried out.
Disable Restart Interlock (for EN3) on Top
The Disable Restart Interlock (for EN3) on Top parameter prevents the restart
interlock being activated if the Release 3 (safety) input changes to Low during a
regular stop of the press. This means that if the Disable Restart Interlock (for EN3)
on Top parameter is configured as Yes and the Enable output changes to Low as a
result of the Top input changing to High, then the Restart required output will not
change to High if the Release 3 (safety) input changes to Low as long as the press
has not been restarted.
Output signals of the function block
Restart required
The Restart required output is High, when a valid restart sequence is expected at the
Restart input.
Sequence/timing diagrams
Chapter 9
246