Mitsubishi Electric WS0-CPU0 Operating Manual page 255

Figure 235:
Sequence/timing diagram
for a complete start
sequence in Standard mode
in two-cycle mode
Figure 236:
Sequence/timing diagram
for a complete start
sequence in Sweden mode
in two-cycle mode
Logic programming – Function blocks
Requirements for the start sequence
If the Enable output changes to Low because of one of the following conditions, a
complete start sequence can be necessary:
 Release 1 (static) is Low,
 the Unexpected PSDI output is High, while Cycle = 0 and there is no active
upstroke muting and no stop at the top dead center,
 in case of a PSDI timeout,
 after the Control of drive has been switched on
If the Unexpected PSDI output is High and the Enable output is Low and the PSDI
input is also Low and Restart interlock is set to Without, a restart is possible without
a complete restart sequence. This can also apply during the press upstroke if Restart
interlock is set to Always.
The minimum break time at the PSDI input is 100 ms or 350 ms. Shorter breaks are
not evaluated as valid, i.e. they are ignored. If the Condition for Release 2 (start)
input is configured as Necessary for first start or as Necessary for every start, the
Release 2 (start) input also must be High if a complete start sequence is required.
After the initial complete start sequence has been executed and the press has
completed a press cycle, the Top input must indicate that the press has currently
reached the top dead center. This is indicated by a rising edge (Low to High) of the
Top input. When this happens, the internal break counter is reset.
A cycle start sequence is required in order to trigger a subsequent cycle. In this case,
the Enable output is set to High when the configured number of breaks has occurred
and the remaining configured conditions have been fulfilled (e.g., Condition for
Release 2 (start) input can be configured as Necessary for every start).
Chapter 9
252