Silicon Graphics ICE X User Manual page 66

3: System Overview
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• Error detection and correction
– External memory transfers are protected by cyclic redundancy check (CRC) error
detection. If a memory packet does not checksum, it is retransmitted.
– Nodes within each blade enclosure exceed SECDED standards by detecting and
correcting 4-bit and 8-bit DRAM failures.
– Detection of all double-component 4-bit DRAM failures occur within a pair of DIMMs.
– 32-bits of error checking code (ECC) are used on each 256 bits of data.
– Automatic retry of uncorrected errors occurs to eliminate potential soft errors.
• Power-on and boot:
– Automatic testing (POST) occurs after you power on the system nodes.
– Processors and memory are automatically de-allocated when a self-test failure occurs.
– Boot times are minimized.
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