Table 6. Mrc Progress Codes - Intel R2000WF series Service Manual

Intel ® Server System R2000WF Product Family System Integration and Service Guide
Early POST Memory Initialization MRC Diagnostic Codes
Memory Initialization at the beginning of POST includes multiple functions, including: discovery, channel
training, validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC Progress Codes are displayed to the Diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Diagnostic LED Decoder
1 = LED On, 0 = LED Off
Upper Nibble
Checkpoint
(Amber)
MSB
8h 4h
MRC Progress Codes
B0h 1 0
B1h 1 0
B2h 1 0
B3h 1 0
B4h 1 0
B5h 1 0
B6h 1 0
B7h 1 0
B8h 1 0
B9h 1 0
BAh 1 0
BBh 1 0
BCh 1 0
BFh 1 0
Should a major memory initialization error occur, preventing the system from booting with data integrity, a
beep code is generated, the MRC will display a fatal error code on the diagnostic LEDs, and a system halt
command is executed. Fatal MRC error halts do NOT change the state of the System Status LED, and they do
NOT get logged as SEL events. The following table lists all MRC fatal errors that are displayed to the
Diagnostic LEDs.
Note: Fatal MRC errors will display POST error codes that may be the same as BIOS POST progress codes
displayed later in the POST process. The fatal MRC codes can be distinguished from the BIOS POST
progress codes by the accompanying memory failure beep code of 3 long beeps as identified in Table 10.

Table 6. MRC Progress Codes

Lower Nibble
(Green)
LSB
2h 1h 8h 4h 2h
1 1 0 0 0
1 1 0 0 0
1 1 0 0 1
1 1 0 0 1
1 1 0 1 0
1 1 0 1 0
1 1 0 1 1
1 1 0 1 1
1 1 1 0 0
1 1 1 0 0
1 1 1 0 1
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
Description
1h
0 Detect DIMM population
1 Set DDR4 frequency
0 Gather remaining SPD data
1 Program registers on the memory controller level
0 Evaluate RAS modes and save rank information
1 Program registers on the channel level
0 Perform the JEDEC defined initialization sequence
1 Train DDR4 ranks
0 Initialize CLTT/OLTT
1 Hardware memory test and init
0 Execute software memory init
1 Program memory map and interleaving
0 Program RAS configuration
1 MRC is done
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