Receiver Output Logic - Ametek UPLC-II System Manual

2.5.2 Receiver Output Logic

2.5.2.1 ON/OFF Receiver Logic/Timers
There is only one logic setting affecting the receiver
in an ON/OFF system and that is a blocking output
hold timer. Typically it is set to disabled (0 ms) and
caution should be taken when using it so that pro-
tective relaying logic such as transient blocking is
not affected.
2.5.2.2 FSK Receiver Output Logic
2-Frequency Directional Comparison Logic
Figure 2–14 illustrates this logic. The logic can be
configured for a typical Direct Transfer Trip or
Directional Comparison Unblock System. To pro-
vide the utmost security, this logic provides for
120ms of guard before trip logic. It requires that
after loss of signal, there must be at least 120ms of
guard before the system is allowed to trip. This may
be disabled or overridden according to system
requirements. Details follow. There is also a 120ms
trip after guard requirement that requires within 120
ms of losing guard that trip is received, otherwise
the channel locks out from tripping.
Hold timers are available for both the trip and guard
outputs that can be set from 1 to 100 ms in 1 ms
increment or be disabled (0 ms). These timers are
on the output side of the logic and therefore only
affect the solid state or electromechanical outputs.
They have no affect on the functionality of the
internal logic.
The pre-trip timer allows for higher security by
delaying the trip output by the time set. It is settable
from 0 to 30 ms in 1 ms increments. Unblock func-
tions will typically be 2 to 8 ms but DTT functions
will typically be on the order of 20 or 30 ms for pre-
trip time. This pre-trip time delay is critical to pro-
viding security against noise causing a false trip and
for every msec added the security increases expo-
nentially.
The logic also provides for line protection of the
transmission line when the remote end's breaker is
open. Upon receiving a trip signal from the other
end for longer than 1000 ms, indicating an open
breaker, the logic disables the guard before trip
requirement such that if the channel is lost and
returns in the trip state, the line relay system will be
allowed to trip for a fault. To allow for this scenario,
January 2016
Chapter 2. Product Description
the guard before trip should be set for "override".
After guard is restored, the logic is reset after 200
ms. Typical line relaying or DTT systems do not
disable guard before trip logic. Unblock logic is
provided in the UPLC-II™ logic to force a trip on
loss of channel. If a fault causes a loss of channel,
there is a window setting between 1 and 500 ms that
will produce a trip output. A setting of 0 ms will dis-
able this feature. After this time, the channel is
locked out from tripping until it receives 120ms of
guard. The assertion of the trip output for unblock
can be delayed by 1 to 100 ms if desired, with a set-
ting of 0 ms disabling this delay. Typical permissive
overreaching transfer trip systems over Power-Line
Carrier take advantage of the Unblock Logic and
are Directional Comparison Unblock systems. A
checkback trip output (meaning trip frequency
received) is provided for testing purposes. The
checkback trip will always assert anytime a trip is
asserted by the logic. However, if a trip frequency
is received after a loss of channel (without guard
return), then only a checkback trip is asserted, and
not an actual trip output.
3-Frequency Directional Comparison Logic
Figure 2–15 illustrates this logic. This logic is sim-
ilar to the 2-frequency logic except with the addi-
tion of logic to handle the Direct Transfer Trip logic
separately, in addition to providing for a Directional
Comparison Unblock System. The Guard Before
Trip and Trip After Guard Logic are duplicated for
the DTT portion as well as the Trip hold and Guard
hold timers. Note that when the 3-frequency system
goes to an Unblock trip, the DTT Guard does not
drop out but the Unblock Guard does. Likewise, on
a DTT Trip, the Unblock Guard does not dropout
but the DTT Guard does.
4-Frequency Directional Comparison Logic
Figure 2–16 illustrates this logic. This logic is like
having two independent sets of the 2-Frequency
logic. In the 2-Frequency logic there are two inputs
to the logic, Guard and Trip. In the 4-Frequency
logic, there are four inputs (frequencies) to the
logic, Guard (F3), CMD A Trip (F4), CMD B Trip
(F2), and CMD A&B Trip (F1). Like in the 3-
Frequency logic, a receipt of CMD A Trip does not
cause the guard for the CMD B to drop out.
Functional block diagrams for these configurations
can be found at the end of this chapter.
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