Ametek UPLC-II System Manual page 113

Table 5–7. Logic Settings for Phase Comparison (FSK Mode)
Channel Trouble
Table 5–8. Logic Settings for 2F Unblock (FSK Mode)
Trip Test
Pre-Trip Delay*
Trip Hold
Unblock Timer
Table 5–9. Logic Settings for 2F POTT/DTT (FSK Mode)
Trip Test
Pre-Trip Delay*
Trip Hold
*
For every msec of pre-trip delay you add, the security, against noise causing a false trip, increases exponentially.
UB & PoTT: a min of 2-4 msec is recommended.
DTT: The time delay should be as long as the critical stability of your system can tolerate, at least 10 msec min.
January 2016
Chapter 5. installation/Commissioning Procedure
Table 5–6. Logic Settings for ON/OFF
(Directional Comparison & Phase Comparison)
Blocking Receiver Drop-out Delay
Priority Start or Stop
Common Start/Stop (KA-4) Enabled or Disabled
Options
Checkback Enabled or Disabled
Receiver Logic
TP & TN
Clamps to "1"
TP & TN
Clamps to "0"
Options
Enabled
or Disabled
Receiver Logic
0 to 30 ms
0 to 100 ms Guard Before Trip
0 to 500 ms Unblock Delay
Options
Enabled
or Disabled
Receiver Logic
0 to 30 ms Guard Hold
0 to 100 ms Guard Before Trip
0 to 15 ms
Polarity HF = TP
& LF = TN
LF = TP
& HF = TN
Guard Hold 0 to 100 ms
None, GBT or GBT
with Override
0 to 100 ms
0 to 100 ms
None, GBT or GBT
with Override
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