Xilinx KCU1250 10GBASE-KR User Manual page 87

Traffic Generator—Monitor Channel 1
Table C-8: Design Version Register (0x4AA1_0000)
Bit Position Mode
4:0
14:5 Read Only
31:16
Table C-9: Ethernet Performance Monitor, Transmit Payload Byte Count Register (0x4AA1_0004)
Bit Position Mode
1:0
Read Only
31:2
Table C-10: Ethernet Performance Monitor, Transmit Packet Count Register (0x4AA1_0008)
Bit Position Mode
1:0
Read Only
31:2
Table C-11: Ethernet Performance Monitor, Received Payload Byte Count Register (0x4AA1_000C)
Bit Position Mode
1:0
Read Only
31:2
Table C-12: Ethernet Performance Monitor, Received Packet Count Register (0x4AA1_0010)
Bit Position Mode
1:0
Read Only
31:2
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Default Value
Ethernet reference design 2.
4'h2
Software version: Indicates the Vivado® Design Suite version
used when developing this reference design. For example,
12'h141
Vivado Design Suite 2014.1 is indicated by 141.
Target Board. KCU1250 board.
16'h1250
Default Value
00 Sample count. Increments once every second.
Transmit payload byte count. This field contains the interface
utilization count for active beats (tx_axis_tready = 1 and
0
tx_axis_tvalid = 1) on channel 1 10G Ethernet MAC AXI4-Stream
interface for transmit.
Default Value
Sample count. Increments once every second.
00
Transmit packet count. This field contains the count for the
event when there is an active beat on channel 1 10G Ethernet
0
MAC AXI4-Stream interface and end of packet (tx_axis_tlast) is
asserted for transmit.
Default Value
Sample count. Increments once every second.
00
Receive payload byte count. This field contains the interface
utilization count for active beats (rx_axis_tready = 1 and
0
rx_axis_tvalid = 1) on channel 1 - 10G Ethernet MAC
AXI4-Stream interface for receive.
Default Value
Sample count. Increments once every second.
00
Receive packet count. This field contains the count for the event
when there is an active beat on channel 1 10G Ethernet MAC
0
AXI4-Stream interface and end of packet (rx_axis_tlast) is
asserted for receive.
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Appendix C: User-Space Registers
Description
Description
Description
Description
Description
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