Xilinx KCU1250 10GBASE-KR User Manual page 75

The Processor System Reset Module IP core provides resets for the MicroBlaze processor
subsystem components and resets to the AXI Interconnect and peripherals (AXI4-Lite
interfaces on AXI UART Lite, Traffic Generator and Monitor, and 10-Gigabit Ethernet MAC
IP). Figure 5-8
X-Ref Target - Figure 5-8
Debouncer
DIP Switch
Logic
Reset
Debouncer
DIP Switch
Reset Logic
Reset to AXI4 Stream Interface
Reset to MAC and PHY
Reset to AXI Lite Interfaces
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
shows the reset connections.
reset_ch1_n
reset ch1
Eyescan
System
reset ch0
CH0 CH0
PHY MAC
reset_ch0_n
peripheral_aresetn
Processor
interconnect_aresetn
System
bus_struct_reset
Reset
mb_reset
MicroBlaze
MicroBlaze
Local
Processor
memory
Figure 5-8: Resets
www.xilinx.com
Chapter 5:
CH0
CH1 CH1
Traffic
PHY MAC
Gen-Mon
AXI
AXI
Interrupt
Interconnect
Controller
Reference Design Details
CH1
Traffic
Gen-Mon
AXI UART
Lite
X18486-120716
75
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