Xilinx KCU1250 10GBASE-KR User Manual page 69

Table 5-3: Ethernet Performance Monitor Parameters and Ports (Cont'd)
Port/Parameter Name
rx_axis_tkeep[7:0]
rx_axis_tlast
rx_axis_tvalid
rx_axis_tuser
rx_axis_tready
Performance Statistics Ports
tx_byte_count
tx_pkt_count
rx_byte_count
rx_pkt_count
User Control and Status Registers
The user selections made in the Ethernet controller application are passed to the Traffic
Generator and Monitor using this block. An AXI4-Lite interface is required for the
MicroBlaze processor subsystem to execute reads (status) and writes (control) to this block.
The AXI4-Lite IP Interface (IPIF) is instantiated in the design to read and write to a register
map file (see the
Providing an AXI4-Lite slave interface provides the flexibility of using this module in other
designs. To reuse this block, the control and status signals into the register map must be
changed. Appendix C, User-Space Registers
Traffic Generator and Monitor block.
X-Ref Target - Figure 5-3
AXI-4 Lite transactions
to and from the
MicroBlaze Processor
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Type
The receive keep signal is used to determine which data bytes are valid
on rx_axis_tdata during a given beat (this signal is valid only if
tx_axis_tvalid and tx_axis_tready are both asserted).
End of frame indicator on received packets. Valid only along with
Input
asser-tion of rx_axis_tvalid.
Source ready to provide data. Indicates that the MAC is presenting valid
Input
data on rx_axis_tdata.
Input If asserted indicates a good packet is received.
Destination ready for receive. Indicates that the loopback is ready to
accept data on rx_axis_tdata.
The simultaneous assertion of rx_axis_tvalid and rx_axis_tready marks
Output
the successful transfer of one data beat on rx_axis_tdata.
The 10-Gigabit Ethernet MAC IP core doesn't look at this signal and
sends received data whenever available.
Output Number of bytes transmitted in one second.
Output Number of packets transmitted in one second.
Output Number of bytes received in one second.
Output Number of packets received in one second.
AXI4-Lite IP Interface (IPIF)
Figure 5-3
AXI4-Lite to IPIF
Figure 5-3: User Register Interface
www.xilinx.com
Chapter 5:
Description
website [Ref 23].
describes the registers implemented in the
shows the user register interface.
Control: Internal traffic generator
selection, payload size, etc.
Status and Control
Register Map
Status: Performance, PHY
status, etc.
Reference Design Details
X18481-120716
69
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