Xilinx KCU1250 10GBASE-KR User Manual page 74

channel 0 156.25 MHz clock. The single ended 156.25 MHz clocks from both channels are
routed to the eye scan system.
X-Ref Target - Figure 5-7
156.25 MHz CH0
MicroBlaze
CH0 Traffic
Subsytem and
Gen-Mon
AXI Interconnect
An external reset (a debounced DIP switch) drives the channel 0 10-Gigabit Ethernet
PCS/PMA IP core, the 10-Gigabit Ethernet MAC IP core and the Processor System Reset IP
core in the processor system. This reset also drives the eye scan system.
Another external reset dip switch drives the Channel 1 10-Gigabit Ethernet PCS/PMA IP
core, the 10-Gigabit Ethernet MAC IP core and the Traffic Generator and Monitor block.
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Figure 5-7 shows the clock distribution.
156.25 MHz
Differential Clock
CH0 MAC CH0 PHY
Eyescan
System
Figure 5-7: Clock Distribution
www.xilinx.com
Chapter 5:
156.25 MHz
Differential Clock
156.25 MHz CH1
CH1 PHY CH1 MAC
Reference Design Details
CH1
AXI
Traffic
UARTLITE
Gen-Mon
X18485-120716
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