Xilinx KCU1250 10GBASE-KR User Manual page 72

Eye Scan System Components
The eye scan system in this reference design is based on application note XAPP1198. Refer
to In-System Eye Scan of a PCI Express Link with Vivado IP Integrator and AXI4 Application
Note (XAPP1198)
AXI DRP Bridge
The AXI DRP bridge receives AXI requests from an AXI master such as the MicroBlaze
processor subsystem. It converts AXI transactions to DRP registers accesses on the
transceiver and routes the result back to the AXI Master. One bridge is required for every
transceiver that performs an eye scan. This reference design has two instances of the AXI
DRP bridge to get eye scan plots on 10-Gigabit Ethernet Channel 0 and Channel 1.
There is also an AXI DRP MUX in the reference design. This allows multiplexing of DRP
accesses between the AXI DRP Bridge and the 10-Gigabit Ethernet PCS/PMA IP Core.
AXI Block RAM Controller
An AXI Slave IP core that allows access to local block RAM by AXI Master devices such as
MicroBlaze processor subsystem and JTAG to AXI Master IP core. The block RAM stores the
data read from the DRP port of the transceiver.
For more details on the AXI Block RAM Controller IP, see the AXI BRAM Controller website
[Ref 28].
JTAG to AXI Master
The JTAG to AXI Master IP core is a customizable core that can generate AXI transactions
and drive AXI signals internal to FPGA. The Vivado logic analyzer Tcl console running on the
control computer interacts with this core through the USB-to-JTAG port on the
KCU1250 board. (Refer to Vivado Design Suite User Guide: Programming and Debugging
(UG908) [Ref 29].) It retrieves data stored in AXI BRAM Controller and passes it to the
control computer.
For more details on the JTAG to AXI Master IP core, see the JTAG to AXI Master website
[Ref 30].
MicroBlaze Processor Subsystem
The MicroBlaze processor subsystem communicates to the transceiver DRP interface
through the AXI to DRP Bridge logic. The software running on the MicroBlaze processor is
derived from code described in Eye Scan with MicroBlaze Processor MCS Application Note
(XAPP743) [Ref
algorithm on the transceiver and stores the data in the AXI block RAM. When the block RAM
is filled with Eye Scan data, the JTAG to AXI IP core reads the data out of the block RAM.
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
[Ref 14] for more information.
31]. The software running on the processor implements the Eye Scan
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