Chapter 5: Reference Design Details; Hardware - Xilinx KCU1250 10GBASE-KR User Manual

Reference Design Details
This chapter describes the hardware design and software components.

Hardware

Figure 5-1 shows a block-level overview of the 10GBASE-KR TRD.
X-Ref Target - Figure 5-1
KCU1250 Board
Java GUI/Driver
and Vivado
Design Suite
To the
UART
Control
Computer
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
XCKU040-2FFGA1156C FPGA
Traffic
Generator
and
Monitor
Traffic
Generator
and
Monitor
AXI DRP
Bridge
AXI DRP
Bridge
AXI BRAM
Controller
BRAM
Eyescan System
Integrated Blocks in FPGA
Xilinx IP
Figure 5-1: 10GBASE-KR TRD Block Diagram
www.xilinx.com
CHANNEL 1 CHANNEL 1
AXI LITE
64 bits at 156.25MHz
10G
MAC
DRP
CHANNEL 0 CHANNEL 0
AXI LITE
64 bits at 156.25MHz
10G
MAC
DRP
AXI-Lite (Master to Slave)
Custom Logic
AXI-Stream
On Board
Chapter 5
SMA
Line
CARD
SMA
Line
CARD
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