Forward Error Correction - Xilinx KCU1250 10GBASE-KR User Manual

3. The scan plots for Channel 0 and Channel 1 are shown in
The Scan Plot for Channel 0 was dragged to a new Vertical group.
NOTE:
X-Ref Target - Figure 3-20

Forward Error Correction

To showcase forward error correction, a 10-Gigabit Ethernet PCS/PMA IP file has been
modified to inject errors in the GTH transceiver parallel data via VIO. The unmodified file is
located at:
<working_directory>/kcu1250_10gbase_kr/hardware/vivado/runs/
impl_run/10gbasekr_trd.srcs/sources_1/bd/mac_phy/ip/
mac_phy_ten_gig_eth_pcs_pma_ch0_0/
synth/mac_phy_ten_gig_eth_pcs_pma_ch0_0_block.v
A demo BIT file is provided with the 10GBASE-KR TRD to inject errors and verify if the
Forward Error Correction (FEC) block is working as expected.
To program the FPGA with this demo:
1. Repeat Set Up the KCU1250
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Figure 3-20: Eye Scan for Channel 0 and Channel 1
Board.
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Chapter 3: Bringing Up the Design
Figure 3-20.
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