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Table 5-1:
Packet Format of Generated Packets
Byte 7
Byte 6
Source Address
Sequence Number
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sequence Number
The source and destination MAC addresses are parameters into this block. The length field
is the data payload value. The actual length of a packet generated by this block is:
•
14 bytes of header (Destination Address + Source Address + Length/Type Field) +
Data payload
The sequence number field indicates packet count and increments by one every packet.
The generated packets are transmitted on AXI4-Stream interface to the 10-Gigabit Ethernet
MAC IP core.
Table 5-2
Table 5-2: Generator Module Parameters and Ports
Port/Parameter Name
XIL_MAC_ID_THIS
XIL_MAC_ID_OTHER
Clock and Reset Ports
reset
tx_axis_clk
Transmit Ports on the AXI4-Stream Interface
tx_axis_tdata[63:0]
tx_axis_tkeep[7:0]
tx_axis_tlast
tx_axis_tvalid
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Byte 5
Byte 4
Length
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
shows the parameters and ports on the generator module.
Type
Source MAC Address
Parameter
For channel 0 = 48'h111100000000
For channel 1 = 48'h222200000000
Destination MAC Address
Parameter
For channel 0 = 48'h222200000000
For channel 1 = 48'h111100000000
Input
Synchronous reset.
Input
156.25 MHz clock transmit ports on the AXI4-Stream interface.
Output
Data to be transmitted to the 10-Gigabit Ethernet MAC IP core.
The transmit keep signal is used to determine which data bytes are valid
on tx_axis_tdata during a given beat (this signal is valid only if
tx_axis_tvalid and tx_axis_tready are both asserted).
Bit 0 corresponds to the least significant byte on tx_axis_tdata and bit 7
corresponds to the most significant byte.
When tx_axis_tlast is not asserted, the only valid value is 0xFF. When
tx_axis_tlast is asserted, valid values are 0x1, 0x3, 0x7, 0xf, 0x1f, 0x3f,
0x7f and 0xff.
End of frame indicator on transmit packets. Valid only along with assertion
Output
of tx_axis_tvalid.
Source ready to provide transmit data. Indicates that the generator is
Output
presenting valid data on tx_axis_tdata.
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Chapter 5:
Reference Design Details
Byte 3
Byte 2
Destination Address
Source Address
Sequence Number
Description
Send Feedback
Byte 1
Byte 0
Sequence Number
66
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