Xilinx KCU1250 10GBASE-KR User Manual page 71

• AXI UART Lite which communicates with the Ethernet Controller application running on
the control computer
• Channel 0 – 10-Gigabit Ethernet MAC IP core
• The Traffic Generator and Monitor connected to channel 0
• Channel 1 – 10-Gigabit Ethernet MAC IP core
• The Traffic Generator and Monitor connected to channel 1
The AXI interconnect enables communication between the MicroBlaze processor subsystem
(Master) and six peripherals (Slaves).
The address range assigned to each peripheral is shown in
driver running on the MicroBlaze processor subsystem will use these addresses to map
read/write transactions from the Ethernet Controller application to the AXI UART Lite to the
MicroBlaze processor subsystem to other peripherals and back.
X-Ref Target - Figure 5-5
For more details on the MicroBlaze processor core, see the MicroBlaze Soft Processor Core
website [Ref 24].
For more details on AXI Interconnect, see the AXI Interconnect website
AXI UART Lite
The AXI UART Lite IP core provides the controller interface for asynchronous serial data
transfer. The Ethernet Controller application running on the control computer
communicates with this serial interface.
The AXI UART Lite IP core also connects to the MicroBlaze processor subsystem through the
AXI interface and passes information to and from the Ethernet Controller application to the
different components of the design.
For more details on AXI UART Lite, see AXI UART Lite LogiCORE IP Product Guide (PG142)
[Ref 26] and the AXI UART Lite website
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Figure 5-5: Peripheral Address Map
[Ref 27].
www.xilinx.com
Chapter 5: Reference Design Details
Figure 5-5. The application
[Ref 25].
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