Xilinx KCU1250 10GBASE-KR User Manual page 26

X-Ref Target - Figure 3-8Add probes to the VIO dashboard
Table 3-1 shows what each VIO window configures and monitors.
Table 3-1: VIO Tab Mapping
VIO Tab
(1)
hw_vio_6 training_*_ch1
(1)
hw_vio_5 training_*_ch0
(1)
hw_vio_4 stat_ch1_*
(1)
hw_vio_3 stat_ch0_*
(1)
hw_vio_2
(1)
hw_vio_1
Notes:
1. The value of n in hw_vio_n might change based on how the Vivado Synthesis tool processes the netlist. You might have to
redo the above mapping accordingly.
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Figure 3-8: Adding a Probe to a VIO Window
Mapping
Configures the DRP port for channel 1 through the training port of the
10-Gigabit Ethernet PCS/PMA IP core.
Configures the DRP port for channel 0 through the training port of the
10-Gigabit Ethernet PCS/PMA IP core.
Monitors the status vector signals of the 10-Gigabit Ethernet PCS/PMA
IP core for channel 1.
Monitors the status vector signals of the 10-Gigabit Ethernet PCS/PMA
IP core for channel 0.
Configures the configuration vector signals of the 10-Gigabit Ethernet
ch1_*
PCS/PMA IP core for channel 1.
Configures the configuration vector signals of the 10-Gigabit Ethernet
ch0_*
PCS/PMA IP core for channel 0.
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