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Xilinx KCU1250 10GBASE-KR User Manual

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KCU1250 10GBASE-KR
Ethernet TRD

User Guide

KUCon-TRD05
Vivado Design Suite
UG1058 (v2017.1) April 19, 2017

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Summary of Contents for Xilinx KCU1250 10GBASE-KR

  • Page 1: User Guide

    KCU1250 10GBASE-KR Ethernet TRD User Guide KUCon-TRD05 Vivado Design Suite UG1058 (v2017.1) April 19, 2017...

  • Page 2: Revision History

    3-9, Figure 3-10, Figure 3-11, Figure 3-18, Figure 3-19, and Figure 3-20. Revised the order of content in the VIO_Tab column in Table 3-2. 03/04/2015 2014.4.1 Initial Xilinx release. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 3: Table Of Contents

    Control and Status Registers ............85 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 4 Xilinx Resources ........

  • Page 5: Chapter 1: Introduction

    10-Gigabit Ethernet PCS/PMA IP core (10GBASE-KR) and the 10-Gigabit Ethernet MAC IP core (10G MAC) and error free traffic flow on this 10-Gigabit Ethernet channel across a backplane. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 6 AXI BRAM Controller BRAM Eyescan System Integrated Blocks in FPGA AXI-Lite (Master to Slave) Custom Logic Xilinx IP AXI-Stream On Board X18426-120716 Figure 1-1: The 10GBASE-KR TRD 10GBASE-KR is defined in IEEE Std 802.3-2012 [Ref 1]. It specifies the 10 Gb/s physical layer specification using 10GBASE-R encoding over an electrical backplane.
  • Page 7 Monitor, and AXI UART Lite using the AXI4-Lite protocol. Drivers running on the MicroBlaze processor subsystem interpret commands ° received from the Ethernet Controller application GUI running on the control computer and convert them to AXI4-Lite transactions. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 8 AXI Interconnect: ° Allows multiple AXI masters (MicroBlaze processor subsystem and JTAG to AXI Master) to communicate with multiple AXI slaves (AXI DRP Bridge and AXI block RAM controller). 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 9 Available Usage (%) CLB LUTs 29,846 242,400 12.31 CLB Registers 41,794 484,800 8.62 Block RAM Tile 6.91 Global Clock Buffers 0.83 BUFG_GT_SYNC 10.90 BUFG_GT 5.00 GTHE3_CHANNEL 10.00 GTHE3_COMMON 40.00 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 10: Chapter 2: Setup

    It can be a laptop or desktop computer with Microsoft Windows 7 Operating system. Design Tools and Software • Vivado Design Suite 2017.1 • USB UART drivers (CP210x VCP drivers) [Ref 6] • Tera Term [Ref 7] 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 11: Preliminary Setup

    Install the USB UART Drivers Download the CP210x USB to UART Bridge VCP drivers (for Windows 7) from Silicon Labs. Follow the instructions in Silicon Labs CP210x USB-to-UART Installation Guide (UG1033) [Ref 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 12 USB UART USB JTAG X18427-120716 Figure 2-1: Connections for Preliminary Setup 3. Power on the KCU1250 board by placing switch SW1 to the ON position. (SW1 in Figure 2-1). 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 13 Bridge: Enhanced COM Port. The Enhanced COM port number must be provided to the Tera Term Pro terminal emulator in step 2, page 15. The Standard COM port number must be provided to the Ethernet Controller application in step 2, page 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 14 9. In the properties window, select the Port Settings tab and set Bits per second, Data bits, Parity, Stop bits, and Flow control to the values shown in (Figure 2-3), and then click OK. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 15: Install Java

    Figure 2-4: Tera Term Pro Settings Install Java Download Java SE Runtime Environment 7 from Oracle [Ref 11] and install the program on the control computer. Follow the installation instructions provided with the software. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 16 2. Right-click either the EthernetController-32-installer (for a 32-bit operating system) or EthernetController-64-installer (for a 64-bit operating system) and select Run as administrator (Figure 2-5). 3. Click Yes in the dialog box that opens. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 17 5. Browse to the location where the Ethernet Controller application will be installed and click Install (Figure 2-7). X-Ref Target - Figure 2-7 X18439-120716 Figure 2-7: Ethernet Controller Installation Location 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 18 To uninstall the Ethernet Controller application after design bring up, open the Control Panel. In TIP: the Control Panel click All Control Panel Items > Programs and Features and uninstall program Xilinx Ethernet Controller - Powered by Xilinx. Ready to Bring Up the Design After all procedures in this chapter are complete, go to Chapter 3, Bringing Up the Design.

  • Page 19: Chapter 3: Bringing Up The Design

    1. Connect the SAMTEC Bulls Eye cables to J41 (GTH Transceiver Quad_226) and J42 (GTH Transceiver Quad_227) as described in this video: New GTX/GTH/GTZ Interconnect on Xilinx Characterization Boards VIDEO: 2. The Bulls Eye SMA cables are numbered. Cable 15 is TX0_P, cable 16 is TX0_N, cable 17 is RX0_P and cable 18 is RX0_N.
  • Page 20 6. Connect one end of the Micro-USB cable to USB-UART port (J1) and the other to the Control PC. 7. Connect one end of the Micro-USB cable to USB-JTAG port (U80) and the other to the Control PC. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 21 X18442-120716 Figure 3-2: KCU1250 Board Connections Including SMA Connections to the Backplane 8. Power on the KCU1250 board by placing switch SW1 to the ON position. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 22: Program The Clocks Sources

    Select option 1 (Set Programmable Clocks): Type 1, and press Enter. 5. Set the Si570 frequency to 156.25 MHz: a. Select option 1 (Set KCU1250 Si570 frequency): Type 1, and press Enter. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 23: Program The Fpga

    Program the FPGA 1. Launch the Vivado® Integrated Design Environment (IDE) on the control computer: a. In Windows, select Start > All Programs > Xilinx Design Tools > Vivado 2017.1 > Vivado 2017.1. b. On the getting started page, click Open Hardware Manager (Figure 3-4).
  • Page 24 3-6). X-Ref Target - Figure 3-6 X18446-120716 Figure 3-6: Select Device to Program d. In the Bitstream file field, browse to the location of the BIT file: <working_dir>/kcu1250_10gbasekr_trd/ready_to_test/kcu1250_10gb asekr_download.bit 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 25: Configure Vio

    3. In the Debug Probes window, right click on hw_vio_1 and select Add probes to VIO Window (Figure 3-8). 4. Repeat the same procedure for hw_vio_2, hw_vio_3, hw_vio_4, hw_vio_5 and hw_vio_6. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 26 Notes: 1. The value of n in hw_vio_n might change based on how the Vivado Synthesis tool processes the netlist. You might have to redo the above mapping accordingly. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 27 Advertise Channel 0 is KR capable: Set value 0080 on ch0_an_adv_data_31_16 e. Advertise Channel 0 supports FEC and is requesting FEC support from the partner: Set value C000 on ch0_an_adv_data_47_32 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 28 Only reset one side of the channel. In this example, only Channel 1 is reset. IMPORTANT: To toggle the VIO signals in the sequence as described in step 6 a Tcl script is provided <working_dir>/kcu1250_10gbasekr_trd/ready_to_test/en_fec_tr_an.tcl 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 29 Bringing Up the Design Source the script in the Tcl console of the Vivado IDE as shown in Figure 3-10. X-Ref Target - Figure 3-10 X18450-120716 Figure 3-10: Source enable_fec_tr_an.tcl 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 30 3-11). It should take only a second or two for 10GBASE-KR IP core to negotiate successfully after executing the script. X-Ref Target - Figure 3-11 X18451-120716 Figure 3-11: AN Complete and KR Negotiated 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 31: Running The Design

    Bringing Up the Design Running the Design Launch the Ethernet Controller Application 1. Launch the Ethernet Controller application GUI on the control computer. In Windows, click Start > All Programs > Xilinx > EthernetController (Figure 3-12). X-Ref Target - Figure 3-12...
  • Page 32 Internal Generator and enter 1500 in the payload field. Click Start. X-Ref Target - Figure 3-14 X18454-120716 Figure 3-14: Set Payload Size on Channel 0 and Channel 1 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 33 Reducing the payload size causes a dip in performance. Refer to Appendix B, Performance Estimates for performance estimation on 10G Ethernet protocol. 2. Stop traffic generation by clicking Stop for both channels. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 34 The TX MAC statistics for Channel 0 should match the RX MAC statistics of ° Channel 1. The TX MAC statistics for Channel 1 should match the RX MAC statistics of ° Channel 0. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 35 1. With traffic running in the Ethernet Controller application, source the run_eyescan.tcl script in the Tcl console of the Vivado IDE (Figure 3-18). The command to source the script is: source <working_dir>/kcu1250_10gbasekr_trd/ready_to_test/eyescan/run_eyescan.tcl. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 36 Do not disconnect the USB-to-JTAG connection. This connection is required for the control IMPORTANT: computer to interact with the JTAG to AXI Master IP core. X-Ref Target - Figure 3-18 X18458-120716 Figure 3-18: Tcl Script run_eyescan.tcl 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 37 Vertical and Horizontal sweeps ° Data sample collection ° Data sample processing to create an eye scan ° X-Ref Target - Figure 3-19 X18459-120716 Figure 3-19: The run_eyescan Command 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 38: Forward Error Correction

    A demo BIT file is provided with the 10GBASE-KR TRD to inject errors and verify if the Forward Error Correction (FEC) block is working as expected. To program the FPGA with this demo: 1. Repeat Set Up the KCU1250 Board. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 39 3. In the Debug Probes window, right click on hw_vio_1 and select Add probes to VIO Window. 4. Repeat the same procedure for hw_vio_2, hw_vio_3, hw_vio_4, hw_vio_5, hw_vio_6, and hw_vio_7. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 40 In the ch1_* and ch0_* windows: Toggle (0 > 1 > 0) ch1_fec_corr_blocks Toggle (0 > 1 > 0) ch1_fec_uncorr_blocks Toggle (0 > 1 > 0) ch0_fec_corr_blocks Toggle (0 > 1 > 0) ch0_fec_uncorr_blocks 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 41 In the Ethernet Controller application, click on Stop and verify Channel 0 MAC statistics and Channel 1 MAC statistics for errors or packet drops. There will be errors and the Frames Received count on the channels will not match up. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 42: Dynamic Reconfiguration Ports

    Source the script in the Tcl console of the Vivado IDE. Refer to UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 15] for a list of DRP addresses that can be accessed. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 43: Chapter 4: Implementing And Simulating The Design

    The 10-Gigabit Ethernet PCS/PMA IP core (10GBASE-KR) requires a license to build the IMPORTANT: design. Obtain the license at the 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR) website [Ref 17]. Click Evaluate or Order to access the license. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 44 1. Launch the Vivado Integrated Design Environment (IDE) and set up the reference design project. • In Windows 7: Click Start > All Programs > Xilinx Design Tools > Vivado 2017.1 > Vivado 2017.1. a. In the Tcl console type: cd <working_dir>/kcu1250_10gbasekr_trd/hardware/vivado source scripts/kcu1250_10GBASEKR_trd.tcl •...
  • Page 45 4-2). Block design mac_phy.bd contains the 10-Gigabit Ethernet MAC IP core (10G MAC), 10-Gigabit Ethernet PCS/PMA IP core (10GBASE-KR), the Traffic Generator and Monitor, and the MicroBlaze™ processor subsystem. Block design 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 46 4. In the No Implementation Results Available window, click Yes. The bitstream will be generated and available at: <working_dir>/kcu1250_10gbasekr_trd/hardware/vivado/runs/impl_run/ 10gbasekr_trd.runs/impl_1/kcu1250_10gbasekr_top.bit. It takes about an hour to build the bitstream. NOTE: 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 47 SDK. To launch SDK with the mac_phy block design exported, in the Tcl console type: (Figure 4-3). source scripts/launch_sdk_mac_phy.tcl X-Ref Target - Figure 4-3 X18464-120716 Figure 4-3: Export Hardware to the SDK 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 48 2. In the SDK window (Figure 4-4) select File > New > Application Project to build an application. X-Ref Target - Figure 4-4 X18465-120716 Figure 4-4: Creating an Application Project in the SDK 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 49 Chapter 4: Implementing and Simulating the Design 3. In the Application Project window (Figure 4-5) enter the project name as kcu1250_10gbasekr_top and click Next. X-Ref Target - Figure 4-5 X18466-120716 Figure 4-5: Assign Project Name 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 50 Chapter 4: Implementing and Simulating the Design 4. Select Empty Application and click Finish (Figure 4-6). X-Ref Target - Figure 4-6 X18467-120716 Figure 4-6: Select Empty Application 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 51 5. In the project explorer tab (Figure 4-7), right-click kcu1250_10gbasekr_top, select Import, and under the General tab select File System. Click Next. X-Ref Target - Figure 4-7 X18468-120716 Figure 4-7: Importing File System 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 52 Select the source directory in the left pane and click Finish (Figure 4-8). The application ELF file will be generated and available at: <working_dir>/kcu1250_10gbasekr_trd/hardware/vivado/runs/impl_run/10gbasekr _trd.sdk/mac_phy/kcu1250_10gbasekr_top/Debug/kcu1250_10gbasekr_top.elf. X-Ref Target - Figure 4-8 X18469-120716 Figure 4-8: Importing Software/Source Directory 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 53 SDK. To launch SDK with eyescan_sys block design exported, type: source scripts/launch_sdk_eyescan.tcl in the Tcl console (Figure 4-9). X-Ref Target - Figure 4-9 X18470-120716 Figure 4-9: Launch the SDK 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 54 2. In the SDK window (Figure 4-10) select File > New > Application Project to build an application. X-Ref Target - Figure 4-10 X18471-120716 Figure 4-10: Building an Application Project in the SDK 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 55 3. In the Application Project window (Figure 4-11) enter the project name as kcu1250_10gbasekr_eyescan and click Next. X-Ref Target - Figure 4-11 X18472-120716 Figure 4-11: Assigning a Project Name in the SDK 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 56 Chapter 4: Implementing and Simulating the Design 4. Select Empty Application and click Finish (Figure 4-12). X-Ref Target - Figure 4-12 X18473-120716 Figure 4-12: Selecting Empty Application 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 57 5. In the project explorer tab (Figure 4-13), right-click kcu1250_10gbasekr_eyescan, select Import, and under the General tab select File System. Click Next. X-Ref Target - Figure 4-13 X18474-120716 Figure 4-13: Importing File System 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 58 Select the source_eyescan directory in the left pane and click Finish (Figure 4-14). The application ELF file will be generated and available at: <working_dir>/kcu1250_10gbasekr_trd/hardware/vivado/runs/impl_run/10gbasekr_t rd.sdk/eyescan/kcu1250_10gbasekr_eyescan/Debug/kcu1250_10gbasekr_eyescan.elf X-Ref Target - Figure 4-14 X18475-120716 Figure 4-14: Selecting the software/source Directory 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 59 X18476-120716 Figure 4-15: Run Script to Create download.bit The create_download_bit.tcl script runs the update_mem command and combines kcu1250_10gbasekr_top.bit, kcu1250_10gbasekr_top.elf and kcu1250_10gbasekr_eyescan.elf into single BIT file available at: <working_dir>/kcu1250_10gbasekr_trd/hardware/vivado/runs/impl_run/ 10gbasekr_trd.runs/impl_1/kcu1250_10gbasekr_download.bit. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 60: Simulating The Design

    The test bench for the 10GBASE-KR TRD is available at: <working_dir>/kcu1250_10gbasekr_trd/hardware/sources/testbench/tb.v. Before running a simulation, the kcu1250_10gbasekr_ref_design project must be open IMPORTANT: step 1 under Generate the Hardware Bitstream must be executed. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 61 X-Ref Target - Figure 4-16 X18477-120716 Figure 4-16: Run ModelSim Simulation To run a simulation using the Vivado Design Suite Simulator: 1. In the Flow Navigator, under Project Manager, click Settings. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 62 Vivado Simulator. click OK in the Project Settings window. X-Ref Target - Figure 4-17 X18478-120716 Figure 4-17: Set Simulator to Vivado Simulator 3. In the Flow Navigator, under Simulation, click Run Simulation > Run Behavioral Simulation. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 63: Chapter 5: Reference Design Details

    Bridge AXI BRAM Controller BRAM Eyescan System Integrated Blocks in FPGA AXI-Lite (Master to Slave) Custom Logic Xilinx IP AXI-Stream On Board X18479-120716 Figure 5-1: 10GBASE-KR TRD Block Diagram 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 64 Virtual Input/Output LogiCORE IP Product Guide (PG159) [Ref 21]. Details about the DRP address map is available in UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 15]. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 65 Ethernet Controller application running on the control computer. Data payload size can be from 46 bytes to 1,500 bytes. Table 5-1 shows the packet format generated by the internal Traffic Generator module. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 66 End of frame indicator on transmit packets. Valid only along with assertion tx_axis_tlast Output of tx_axis_tvalid. Source ready to provide transmit data. Indicates that the generator is tx_axis_tvalid Output presenting valid data on tx_axis_tdata. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 67 • RX Payload Byte Count. This counter counts bytes transferred when rx_tvalid and rx_tready signals are asserted between the Traffic Generator block and the 10G MAC. At 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 68 The simultaneous assertion of tx_axis_tvalid and tx_axis_tready marks the successful transfer of one data beat on tx_axis_tdata. Receive Ports on the AXI4-Stream Interface rx_axis_tdata[63:0] Input Data received by the 10-Gigabit Ethernet MAC IP core. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 69 AXI-4 Lite transactions Status and Control AXI4-Lite to IPIF to and from the Register Map MicroBlaze Processor Status: Performance, PHY status, etc. X18481-120716 Figure 5-3: User Register Interface 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 70 The 10GBASE-KR TRD AXI interconnect IP is reconfigured to have six master ports instead of one. The six master ports connect to six AXI slaves: • AXI interrupt controller 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 71 For more details on AXI UART Lite, see AXI UART Lite LogiCORE IP Product Guide (PG142) [Ref 26] and the AXI UART Lite website [Ref 27]. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 72 AXI block RAM. When the block RAM is filled with Eye Scan data, the JTAG to AXI IP core reads the data out of the block RAM. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 73 10-Gigabit Ethernet MAC and Traffic generator on Channel 0. A similar clock circuit is implemented for Channel 1. The MicroBlaze processor subsystem is driven by the 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 74 This reset also drives the eye scan system. Another external reset dip switch drives the Channel 1 10-Gigabit Ethernet PCS/PMA IP core, the 10-Gigabit Ethernet MAC IP core and the Traffic Generator and Monitor block. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 75 Reset to MAC and PHY Processor interconnect_aresetn Reset to AXI Lite Interfaces System bus_struct_reset Reset mb_reset MicroBlaze MicroBlaze AXI UART Local Interrupt Processor Interconnect Lite memory Controller X18486-120716 Figure 5-8: Resets 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 76: Software

    Throughput numbers and graphs when a test is executing • 10-Gigabit Ethernet MAC IP statistics • Power consumption and temperature for the FPGA • Block diagram of the design 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 77: Command Format

    Read Command R <type of request> <output type> <Command number, denoted as a 4-character hexadecimal numeric string, AAAA> • R denotes a Read command 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 78 Write Command W <Command Number denoted as a 4-character hexadecimal numeric string AAAA> < Data, represented as an 8-character hexadecimal numeric string DDDDDDDD> • W denotes a Write command 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 79 Send to Client on Host Side Command Interpreter Command Number to Array Index Mapping Integer Array UART Driver Containing All Register Offsets X18489-120716 Figure 5-11: Software Layers in the MicroBlaze Processor Server Application 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 80 6. The Command Interpreter identifies the register offset value in the integer array, with respect to the command number associated with the request. 7. The Command Interpreter functionality is different for Single Read and Bulk Read commands. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 81 Processor MCS Application Note (XAPP743) and In-System Eye Scan of a PCI Express Link with [Ref 14] Vivado IP Integrator and AXI4 Application Note (XAPP1198) and are not covered in this document. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 82: Appendix A: Directory Structure

    The directory structures for the 10GBASE-KR TRD is shown in Figure A-1. X-Ref Target - Figure A-1 uc1250_10gbasekr_trd software hardware ready_to_test readme source sources ip_packaged constraints testbench vivado scripts X18425-120716 Figure A-1: Targeted Reference Design Directory Structure 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 83: Directory Content Summary

    Contains the bit file to program the KCU1250 characterization board. readme A TXT file that describes the 10GBASE-KR TRD and includes revision history information. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 84 Payload size/Packet size * 100 (Gb/s) 64/(38 + 64) = 62.7% 6.27 512/(38 + 512) = 93.1% 9.31 1024 1024/(38 + 1024) = 96.3% 9.63 1500 1500/(38 + 1500) = 97.5% 9.75 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 85: Appendix C: User-Space Registers

    Indicates the Vivado® Design Suite version used when 15:4 Read Only developing this reference design. For example, Vivado Design 12’h141 Suite 2014.1 is indicated by 141. 31:16 Target Board: KCU1250 board. 16’h1250 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 86 Ethernet frame data payload size. Allowed values (46 bytes to 31:16 d'125 1,500 bytes). Table C-7: PHY status Register (0x4AA0_00x18) Bit Position Mode Default Value Description Read Only PHY is up. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 87 Receive packet count. This field contains the count for the event Read Only when there is an active beat on channel 1 10G Ethernet MAC 31:2 AXI4-Stream interface and end of packet (rx_axis_tlast) is asserted for receive. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...
  • Page 88 Ethernet frame. Data payload size allowed values = 46 bytes to 31:16 d'125 1,500 bytes. Table C-14: status Register (0x4AA1_00x18) Bit Position Mode Default Value Description Read Only PHY is up. 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 89: Xilinx Resources

    For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. Solution Centers See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips. References...
  • Page 90 31. Eye Scan with MicroBlaze Processor MCS Application Note (XAPP743) 32. UltraScale Architecture System Monitor User Guide (UG580) 33. AXI4-Lite IPIF LogiCORE IP Product Guide (PG155) 34. System Management Wizard LogiCORE IP Product Guide (PG185) 10GBASE-KR Ethernet TRD Send Feedback UG1058 (v2017.1) April 19, 2017 www.xilinx.com...

  • Page 91: Training Resources

    Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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