Xilinx KCU1250 10GBASE-KR User Manual page 70

Control Plane Components
The Ethernet Controller application running on the control computer sends control
information and receives status to and from different components of the 10GBASE-KR TRD
using the MicroBlaze processor subsystem.
MicroBlaze Processor Subsystem and AXI Interconnect
The IP cores required to support the MicroBlaze processor and create a subsystem are:
• MicroBlaze local memory
• Processor system reset
• MicroBlaze debug module
• AXI Interrupt controller
In Vivado IPI, adding the MicroBlaze IP core and running the connection automation creates
the MicroBlaze processor system shown in
X-Ref Target - Figure 5-4
The AXI interconnect IP allows the MicroBlaze processor subsystem to communicate with
the AXI Interrupt controller IP using the AXI4 memory mapped interface.
The 10GBASE-KR TRD AXI interconnect IP is reconfigured to have six master ports instead
of one. The six master ports connect to six AXI slaves:
• AXI interrupt controller
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Figure 5-4: IPI-Generated MicroBlaze Processor System
www.xilinx.com
Chapter 5:
Figure 5-4.
Reference Design Details
X18482-120716
70
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