Appendix C: User-Space Registers; Control And Status Registers - Xilinx KCU1250 10GBASE-KR User Manual

User-Space Registers
User space registers are user-defined registers implemented in the Traffic Generator and
Monitor block shown in
processor subsystem via the AXI4-Lite interface.
Table C-1 through
10GBASE-KR TRD. All registers are 32 bits wide. Register bit positions are to be read from bit
31 to bit 0 from left to right. All bits that are undefined in this section are reserved and will
return zero when read. Address holes will also return a value of zero when read.
Each peripheral connected to the MicroBlaze processor subsystem is assigned an offset
address which is the base address for that peripheral.
assigned to the Traffic Generator and Monitor blocks (eth_axi_stream_gen_mon_0 and
eth_axi_stream_gen_mon_1). The Traffic Generator and Monitor base addresses are:
• Traffic Generator and Monitor channel 0: 0x4AA0_0000
• Traffic Generator and Monitor channel 1: 0x4AA1_0000

Control and Status Registers

Traffic Generator—Monitor Channel 0
Table C-1: Design Version Register (0x4AA0_0000)
Bit Position Mode
3:0
15:4 Read Only
31:16
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Figure 5-1. These registers can be accessed by the MicroBlaze™
Table C-14 describe the custom registers implemented in the
Default Value
Ethernet reference design 2.
4'h2
Indicates the Vivado® Design Suite version used when
developing this reference design. For example, Vivado Design
12'h141
Suite 2014.1 is indicated by 141.
Target Board: KCU1250 board.
16'h1250
www.xilinx.com
Appendix C
Figure 5-5 shows the addresses
Description
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