Xilinx KCU1250 10GBASE-KR User Manual page 40

Table 3-2 shows what each VIO dashboard configures and monitors.
Table 3-2: VIO Dashboard Mapping for the FEC and Error Injection BIT File
VIO Dashboard
(1)
hw_vio_7
(1)
hw_vio_6
(1)
hw_vio_5
(1)
hw_vio_4
(1)
hw_vio_3
(1)
hw_vio_2
(1)
hw_vio_1
Notes:
1. The value of n in hw_vio_n might change based on how the Vivado Synthesis tool processes the netlist. You might
have to redo the above mapping accordingly.
5. Verify if stat_ch0_pcs_rx_link_status and stat_ch1_pcs_rx_link_status is 1. This indicates
that the 10GBASE-R link is up.
6. Enter the following Tcl script in the Vivado IDE to enable FEC, Training and Auto
Negotiation on both channels:
source <working_dir>/kcu1250_10gbasekr_trd/ready_to_test/enable_fec_tr_an.tcl
7. Verify if Auto Negotiation is complete (stat_ch*_an_complete) and 10GBASE-KR is
negotiated successfully (stat_ch*_bp_KR_negotiated) in stat_ch0* and stat_ch1* VIO
windows.
8. Repeat the steps in
9. In the ch1_* and ch0_* VIO windows, follow this sequence to insert errors in the data
stream:
a. In the ch1_* and ch0_* windows:
- Toggle (0 > 1 > 0) ch1_fec_corr_blocks
- Toggle (0 > 1 > 0) ch1_fec_uncorr_blocks
- Toggle (0 > 1 > 0) ch0_fec_corr_blocks
- Toggle (0 > 1 > 0) ch0_fec_uncorr_blocks
10GBASE-KR Ethernet TRD
UG1058 (v2017.1) April 19, 2017
Mapping
Configures the DRP port for channel 1 through the training
training_*_ch1
port of 10G Ethernet PCS-PMA IP.
Configures the DRP port for channel 0 through the training
training_*_ch0
port of 10G Ethernet PCS-PMA IP.
Monitors the status vector signals of 10G Ethernet PCS-PMA
stat_ch1_*
IP for channel 1.
Monitors the status vector signals of 10G Ethernet PCS-PMA
stat_ch0_*
IP for channel 0.
Configures the configuration vector signals of 10G Ethernet
ch1_*
PCS-PMA IP for channel 1.
Configures the configuration vector signals of 10G Ethernet
ch0_*
PCS-PMA IP for channel 0.
Allows insertion of bit errors in transmit and receive data
insert_*_bit_error_*
streams of Channel 0.
Running the Design.
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Chapter 3: Bringing Up the Design
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