Related Manuals for Xilinx LogiCORE
Summary of Contents for Xilinx LogiCORE
- Page 1 LogiCORE™ Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Getting Started Guide UG145 January 18, 2006...
- Page 2 Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
- Page 3 Initial Xilinx release. 04/28/05 Updated to version 6.0 of the core, and Xilinx Tools v7.1i SP2. 01/18/06 Updated to version 7.0 of the core, and Xilinx Tools v8.1i, updated Licensing chapter. Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006...
- Page 4 Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006...
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Page 5: Table Of Contents
..............22 Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... - Page 6 Customizing the Test Bench ..........49 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0...
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Page 7: Schedule Of Figures
LogiCORE in SGMII mode ........ - Page 8 Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006...
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Page 9: Preface: About This Guide
Preface About This Guide The LogiCORE™ Ethernet 1000Base-X PCS/PMA or SGMII v7.0 Getting Started Guide provides information about generating an Ethernet 1000BASE-X PCS/PMA core, customizing and simulating the core using the provided example designs, and running the design files through implementation using the Xilinx tools. -
Page 10: Conventions
Problem Solvers Interactive tools that allow you to troubleshoot your design issues http://www.xilinx.com/support/troubleshoot/psolvers.htm Tech Tips Latest news, design tips, and patch information for the Xilinx design environment http://www.xilinx.com/xlnx/xil_tt_home.jsp Conventions This document uses the following conventions. An example illustrates each convention. -
Page 11: Online Document
Refer to “Title Formats” in document Chapter 1 for details. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... - Page 12 Preface: About This Guide www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006...
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Page 13: Chapter 1: Introduction
About the Core The Ethernet 1000BASE-X PCS/PMA or SGMII core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see http://www.xilinx.com/systemio/1gbsx_phy/index.htm. For information about system requirements, installation, and licensing options, see Chapter 2, “Installing... -
Page 14: Technical Support
For technical support, see http://support.xilinx.com/. Questions are routed to a team of engineers with expertise using the Ethernet 1000BASE-X PCS/PMA or SGMII core. Xilinx will provide technical support for use of this product as described in the Xilinx Ethernet 1000BASE-X PCS/PMA or the Xilinx SGMII User Guide and the Ethernet 1000BASE- X PCS/PMA or SGMII Getting Started Guide. -
Page 15: Chapter 2: Installing And Licensing The Core
• Xilinx ISE 8.1i Before You Begin Before installing the core, you must have a Xilinx.com account and the ISE 8.1i software installed on your system. If you have already completed these steps, go to “Installing the Core.” Click Login at the top of the Xilinx home page;... -
Page 16: Core Generator Ip Updates Installer
$XILINX/bin/lin/unzip -d $XILINX ise_81i_ip_update1.zip − Solaris. From a UNIX shell, type the following: $XILINX/bin/sol/unzip -d $XILINX ise_81i_ip_update1.zip To verify the root directory of your Xilinx installation, do one of the following: − Windows. Type from a DOS prompt. echo %XILINX% −... -
Page 17: Verifying The Installation
Determine if the installation was successful by verifying that the new core or cores appear in the CORE Generator GUI. For additional assistance installing the IP Update, contact www.xilinx.com/support. License Options The Ethernet 1000BASE-X PCS/PMA or SGMII core has the following two licensing options. -
Page 18: Simulation Only
Chapter 2: Installing and Licensing the Core Simulation Only The Simulation Only Evaluation license is provided by default with the Xilinx CORE Generator and requires no electronic license key. This license lets you assess the core functionality with either the provided example design or alongside your own design and demonstrates the various interfaces to the core in simulation. -
Page 19: Chapter 3: Quick Start Example Design
The quick start steps provided in this chapter let you quickly generate an Ethernet 1000BASE-X PCS/PMA or SGMII core, run the design through implementation with the Xilinx tools, and simulate the design using the provided demonstration test bench. For detailed information about the example design, see Chapter 4, “Detailed Example... -
Page 20: Generating The Core
For general help with starting and using CORE Generator on your system, see the documentation supplied with ISE, including the Core Generator Guide. These documents can be downloaded from: http://www.xilinx.com/support/software_manuals.htm. Create a new project. For project options, select the following:... -
Page 21: Implementing The Example Design
Note: Available only with a Full license. After the core is generated, the netlists and example design can be processed by the Xilinx implementation tools. The generated output files include several scripts to assist you in running the Xilinx software. -
Page 22: Timing Simulation
This section contains instructions for running a timing simulation or the Ethernet 1000BASE-X PCS/PMA or SGMII core using either VHDL or Verilog. A timing simulation model is generated when run through the Xilinx tools using the implementation script. You must implement the core before attempting to run timing simulation. -
Page 23: Directory Structure And File Descriptions
This chapter provides detailed information about the Ethernet 1000BASE-X PCS/PMA or SGMII example design, including a description of files and the directory structure generated by the Xilinx CORE Generator, the purpose and contents of the provided scripts, the contents of the example HDL wrappers, and the demonstration test bench. - Page 24 Chapter 4: Detailed Example Design Project Directory (<project_dir>) <component_name>.ngc The Xilinx netlist for the core. This is instantiated by the VHDL example design. <component_name>.vhd The VHDL simulation model used to support the VHDL functional simulation of the core. This is UNISIM based.
- Page 25 <project_dir>/implement Note: This directory is only present with the Full license. implement.sh A UNIX shell script that processes the example design through the Xilinx tool flow. See “Implementation Scripts,” page 30 for more information. implement.bat A Windows batch file that process the example design through the Xilinx tool flow. See “Implementation Scripts,”...
- Page 26 An IUS script file that compiles the VHDL sources and then runs the timing simulation to completion. wave_ncsim.sv An IUS macro file that opens a wave window and adds signals of interest to it. It is called by the simulate_ncsim.sh script file. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006...
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Page 27: Verilog Design Entry
Figure 4-2: Core Directories and Files Project Directory (<project_dir>) <component_name>.ngc The Xilinx netlist for the core. This is instantiated by the VHDL example design. <component_name>.v The Verilog simulation model used to support the Verilog functional simulation of the core. This is UNISIM-based. - Page 28 <project_dir>/implement Note: This directory is only present with the Full license. implement.sh A UNIX shell script that processes the example design through the Xilinx tool flow. See “Implementation Scripts,” page 30 for more information. implement.bat A Windows batch file that process the example design through the Xilinx tool flow. See “Implementation Scripts,”...
- Page 29 <project_dir>/implement/results This directory is produced by the implementation scripts and is used to run through the example design and the core through the Xilinx implementation tools. Once the implement script has completed it contains the following files for timing simulation.
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Page 30: Implementation Scripts
Design Entry project setting) and timing information in the form of SDF files. The Xilinx tool flow generates several output and report files. These are saved in the following directory which is created by the implement script: <project_dir>/<component_name>/implement/results... -
Page 31: Timing Simulation
Compiles the demonstration test bench • Starts a simulation of the test bench • Opens a Wave window and adds signals of interest (wave_mti.do/wave_ncsim.sv) • Runs the simulation to completion Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... -
Page 32: Core Example Design Using Rocketio
A transmitter elastic buffer • GMII interface logic, including IOB and DDR registers instances, where required • Input and output buffers for other port signals of the top level www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006... -
Page 33: Transceiver
When the GMII is used as an internal interface, it is expected that the entire interface will be synchronous to a single clock domain and the Transmitter Elastic Buffer should be discarded. See the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide for information about connecting the core to an internal GMII or an Ethernet MAC. -
Page 34: Demonstration Test Bench
Core with MDIO Interface The demonstration test bench performs the following tasks: • Input clock signals are generated. • A reset is applied to the example design. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006... -
Page 35: Customizing The Test Bench
New frames can be added by defining a new frame of data. Modified frames are automatically updated in both stimulus and monitor functions. Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... -
Page 36: Core Example Design With Ten-Bit Interface
When the MDIO interface option is selected, the core can be reconfigured by editing the injected MDIO frame in the demonstration test bench. See the Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide for more information on using the MDIO interface. -
Page 37: Transmitter Elastic Buffer
Transmitter Elastic Buffer should be discarded. See the Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide for information about connecting the core to an internal GMII (for example, an Ethernet MAC). -
Page 38: Demonstration Test Bench
The Ethernet 1000BASE-X PCS/PMA core is configured through the MDIO interface by injecting an MDIO frame into the example design. This disables Auto-Negotiation (if present) and takes the core out of the Isolate state. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006... -
Page 39: Customizing The Test Bench
Frames can be added by defining a new frame of data. Any modified frames are automatically updated in both stimulus and monitor functions. Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... -
Page 40: Sgmii Example Design / Dynamic Switching Example Design
If the MDIO interface option has been selected, the core can be reconfigured by editing the injected MDIO frame in the demonstration test bench. See the Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide for more information about using the MDIO interface. -
Page 41: Transceiver
For Virtex-4 FX devices only, a Calibration Block is required. See the Calibration Block Users Guide for more information. This is decribed in the following files: VHDL project_dir/<component_name>/example_design/cal_block_v1_2_1.vhd Verilog project_dir/<component_name>/example_design/cal_block_v1_2_1.v Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... -
Page 42: Figure 4-8: Sgmii Adaptation Module
125 MHz), but it does allow a straightforward internal connection to an Ethernet MAC core. For example, the SGMII adaptation module can be used to interface the Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE, operating in SGMII mode, to the Xilinx Tri-Mode Ethernet MAC LogiCORE (see the Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide for more information). -
Page 43: Clock Generation
SGMII reference clock, sgmii_clk. At 10 Mbps, this signal is valid for a single period of clk125m every one hundred clocks and again marks the falling edge Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... -
Page 44: Johnson Counter
Chapter 4: Detailed Example Design sgmii_clk. This clock enable signal is used as the control for the data byte repetition in the Transmitter and Receiver Rate Adaptation modules. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006... -
Page 45: Transmitter Rate Adaptation Module
(result of IOB output DDR) Figure 4-9: Clock Generator Output Clocks and Clock Enable Johnson Counter The Johnson Counter is described in the following files: VHDL project_dir>/<component_name>/example_design/sgmii_adapt/ johnson_cntr.vhd Verilog project_dir>/<component_name>/example_design/sgmii_adapt/ johnson_cntr.v Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... -
Page 46: Receiver Rate Adaptation Module
10 times when operating at a speed of 100 Mbps and 100 times when operating at a speed of 10 Mbps. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006... - Page 47 At 1 Gbps, the data is valid on every clock cycle of the 125 MHz reference clock (clk125m). Data received from the core is clocked straight through the Receiver Rate Adaptation module. Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006...
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Page 48: Demonstration Test Bench
D0 D0 D0 D1 D1 D1 D1 D1 D1 D1 D1 D1 D2 D2 D2 sgmii_clk_en_fall gmii_txd_out[7:0] 10 clk125 m cycles sgmii_clk Figure 4-11: Receiver Rate Adaptation Module Data Sampling www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006... -
Page 49: Customizing The Test Bench
MDIO frame into the example design. This disables Auto-Negotiation and takes the core out of Isolate state. • The following frames are injected into the GMII transmitter by the GMII stimulus block at 1 Gbps. Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006... -
Page 50: Customizing The Test Bench
Determine the configurations that can safely be used with the test bench. The core can be reconfigured by editing the injected MDIO frame in the demonstration test bench. See the Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide for information about using the MDIO interface. - Page 51 SGMII Example Design / Dynamic Switching Example Design 100 Mbps operation set speed_is_10_100 to logic 1 set speed_is_100 to logic 1 10 Mbps operation set speed_is_10_100 to logic 1 set speed_is_100 to logic 0 Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 www.xilinx.com UG145 January 18, 2006...
- Page 52 Chapter 4: Detailed Example Design www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 UG145 January 18, 2006...