STMicroelectronics STM32F042G4 Manual page 84

Electrical characteristics
Symbol Parameter
(2)
f External trigger frequency
TRIG
V
Conversion voltage range
AIN
(2)
R External input impedance
AIN
Sampling switch
(2)
R
ADC
resistance
Internal sample and hold
(2)
C
ADC
capacitor
(2)
Calibration time
t
CAL
ADC_DR register write
(2)
W
LATENCY
latency
(2)
t Trigger conversion latency
latr
ADC jitter on trigger
Jitter
ADC
conversion
(2)
Sampling time
t
S
(2)
t Power-up time
STAB
Total conversion time
(2)
t
CONV
(including sampling time)
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 μA on I
on I should be taken into account.
DD
2. Guaranteed by design, not tested in production.
Equation 1: R

R
AIN
84/117
Table 54. ADC characteristics (continued)
f
ADC
See
Table 55
f
ADC
ADC clock = HSI14
ADC clock = PCLK/2
ADC clock = PCLK/4
f = f
ADC
f
f = f
ADC
f
f
ADC
f
ADC
f
ADC
max formula
AIN
T
S
------------------------------------------------------------- - R
N +
  
f C ln 2
ADC ADC
DocID025832 Rev 2
Conditions
= 14 MHz
Equation 1 and
for details
= 14 MHz
1.5 ADC
cycles + 2
f
PCLK
/2 = 14 MHz
PCLK
= f /2
ADC PCLK
/4 = 12 MHz
PCLK
= f /4
ADC PCLK
= f = 14 MHz
HSI14
f = f
ADC HSI14
= 14 MHz
= 14 MHz
14 to 252 (t
successive approximation)
–
ADC
2

Min Typ Max
- - 823
- -
0 - V
- -
- -
- -
5.9
83
1.5 ADC
cycles + 3
-
f
cycles
PCLK
- 4.5
- 8.5
0.196
5.5
0.219
10.5
0.188 - 0.259
- 1
0.107 - 17.1
1.5 - 239.5
0 0
1 -
for sampling +12.5 for
S
STM32F042xx
Unit
kHz
17 1/f
ADC
V
DDA
50 k
1 k
8 pF
μs
1/f
ADC
cycles
f
PCLK
-
cycle
f
PCLK
-
cycle
μs
1/f
PCLK
μs
1/f
PCLK
μs
- 1/f
HSI14
μs
1/f
ADC
1 μs
18 μs
1/f
ADC
and 60 μA
DDA