High-Definition Multimedia Interface (Hdmi) - Consumer; Electronics Control (Cec); Controller Area Network (Can); Universal Serial Bus (Usb) - STMicroelectronics STM32F042G4 Manual

STM32F042xx
3.17

High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.18

Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.19

Universal serial bus (USB)

The STM32F042x embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up-to 1 KB (the last 256 bytes are used for CAN peripheral if
enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be
generated from the internal main PLL (the clock source must use an HSE crystal oscillator)
or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this
oscillator can be taken from the USB data stream itself (SOF signalization) which allows
crystal-less operation.
3.20

Clock recovery system (CRS)

The STM32F042x embeds a special block which allows automatic trimming of the internal
48 MHz oscillator to guarantee its optimal accuracy over the whole device operational
range. This automatic trimming is based on the external synchronization signal, which could
be either derived from USB SOF signalization, from LSE oscillator, from an external signal
on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.21

Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
DocID025832 Rev 2
Functional overview
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