ZiLOG Z80380 User Manual page 76

Z
ILOG
DAA
DECIMAL ADJUST ACCUMULATOR
DAA
← Decimal Adjust A
Operation: A
The accumulator is adjusted to form two 4-bit BCD digits following a binary, two's
complement addition or subtraction on two BCD-encoded bytes. The table below indicates
the operation performed for addition (ADD, ADC, INC) or subtraction (SUB, SBC, DEC,
NEG).
C
Before
Operation DAA
0
0
ADD 0
ADC 0
INC 0
(N=0) 0
1
1
1
SUB
SBC 0
DEC 0
NEG 1
(N=1) 1
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if the result is zero; cleared otherwise
H: See table above
P: Set if the parity of the result is even; cleared otherwise
N: Not affected
C: See table above
Addressing
Mode Syntax
DAA
5-42
Hex Value H
Upper Digit Before
(Bits 7-4) DAA
0-9 0
0-8 0
0-9 1
A-F 0
9-F 0
A-F 1
0-2 0
0-2 0
0-3 1
0-9 0
0-8 1
7-F 0
6-F 1
Instruction Format
00100111
Hex Value Number
Lower Digit Added
(Bits 3-0) to Byte
0-9 00
A-F 06
0-3 06
0-9 60
A-F 66
0-3 66
0-9 60
A-F 66
0-3 66
0-9 00
6-F FA
0-9 A0
6-F 9A
Execute
Time
3
C H
After After
DAA DAA
0 0
0 1
0 0
1 0
1 1
1 0
1 0
1 1
1 0
0 0
0 1
1 0
1 1
Note
DC-8297-03
Z380 ™
U ' M
SER S ANUAL