ZiLOG Z80380 User Manual page 211

Z
ILOG
TST src
Operation: A AND src
A logical AND operation is performed between the corresponding bits of the source operand
and the accumulator. The contents of both the accumulator and the source are unaffected;
only the flags are modified as a result of this instruction.
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if all bits of the result are zero; cleared otherwise
H: Set
P: Set if the parity is even; cleared otherwise
N: Cleared
C: Cleared
Addressing
Mode Syntax
R: TST R
IM: TST n
TST (HL)
IR:
Field Encodings: r: per convention
DC-8297-03
src = R, IM, IR
Instruction Format
11101101 00-r-100
11101101 01100100 ——n—
11101101 00110100
TEST (BYTE)
Execute
Time Note
2
2
2+r
™
Z380
U ' M
SER S ANUAL
TST
5-177