ZiLOG Z80380 User Manual page 191

Z
ILOG
RRD
Operation: tmp(3-0)
A(3-0)
dst(3-0)
dst(7-4)
The low digit of the accumulator is logically concatenated to the destination byte whose
memory address is in the HL register. The resulting three-digit quantity is rotated to the right
by one BCD digit (four bits). The upper digit of the source is moved to the lower digit of the
source; the lower digit of the source is moved to the lower digit of the accumulator, and the
lower digit of the accumulator is moved to the upper digit of the source. The upper digit of
the accumulator is unaffected. In multiple-digit BCD arithmetic, this instruction can be used
to shift to the right a string of BCD digits, thus dividing it by a power of ten. The accumulator
serves to transfer digits between successive bytes of the string. This is analogous to the use
of the Carry flag in multiple-precision shifting using the RR instruction.
Flags: S: Set if the accumulator is negative after the operation; cleared otherwise
Z: Set if the accumulator is zero after the operation; cleared otherwise
H: Cleared
P: Set if the parity of the accumulator is even after the operation; cleared otherwise
N: Cleared
C: Unaffected
Addressing
Mode Syntax
RRD
DC-8297-03
← A(3-0)
← dst(3-0)
← dst(7-4)
← tmp(3-0)
Instruction Format
11101101 01100111
ROTATE RIGHT DIGIT
Execute
Time Note
3+r
™
Z380
U ' M
SER S ANUAL
RRD
5-157