ZiLOG Z80380 User Manual page 223

Z
ILOG
Table 7-1. Effect of a Reset on Z380 CPU and Related I/O Registers
Register
Program Counter
Stack Pointer
I
R
Select Register
A and F Registers
Register Extensions
I/O Bus Control Register 0
Interrupt Enable Register
Assigned Vector Base Register
Trap and Break Register
Reset Value
00000000
00000000
000000
00
00000000
0000
00
01
00
00
Comments
PCz, PC
SPz, SP
Iz, I
Register Bank 0 Selected:
AF, Main Bank, IX, IY
Native Mode
Maskable Interrupts Disabled, in Mode 0
Bus Request Lock-Off
Register Banks 3-0:
A, F, A', F' Unaffected
Register Bank 0:
BCz, DEz, HLz, IYz,
BCz', DEz', HLz', IYz'
(All "non-extended" portions unaffected.)
Register Bank 3-1 Unaffected.
IOCLK = BUSCLK/8
/INT0 Enabled
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