ZiLOG Z80380 User Manual page 146

Z
ILOG
ORW
OR (WORD)
ORW [HL,]src
Operation: HL(15-0)
A logical OR operation is performed between the corresponding bits of the source operand
and the HL register and the result is stored in the HL register. A 1 bit is stored wherever either
of the corresponding bits in the two operands is 1; otherwise a 0 bit is stored. The contents
of the source are unaffected.
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if all bits of the result are zero; cleared otherwise
H: Cleared
P: Set if the parity is even; cleared otherwise
N: Cleared
C: Cleared
Addressing
Mode Syntax
R: ORW [HL,]R
RX: ORW [HL,]RX
ORW [HL,]nn
IM:
X: ORW [HL,](XY+d)
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y: 0 for IX, 1 for IY
5-112
src = R, RX, IM, X
← HL(15-0) OR src(15-0)
Instruction Format
11101101 101101rr
11y11101 10110111
11101101 10110110 -n(low) -n(high)-
11y11101 11110110 ——d—
U '
SER S
Execute
Time Note
2
2
2+r
4+r I
DC-8297-03
Z380 ™
M
ANUAL