ZiLOG Z80380 User Manual page 207

Z
ILOG
SUB HL,src
Operation: if (XM) then begin
HL(31-0)
end
else begin
HL(15-0)
end
The source operand is subtracted from the HL register and the difference is stored in the
HL register. The contents of the source are unaffected. Two's complement subtraction is
performed. Note that the length of the operand is controlled by the Extended/Native mode
selection, which is consistent with the manipulation of an address by the instruction.
S: Unaffected
Flags:
Z: Unaffected
H: Set if there is a borrow from bit 12 of the result; cleared otherwise
V: Unaffected
N: Set
C: Set if there is a borrow from the most significant bit of the result; cleared otherwise
Addressing
Mode Syntax
DA: SUB HL,(nn)
DC-8297-03
src = DA
←
HL(31-0) - src(31-0)
←
HL(15-0) - src(15-0)
Instruction Format
11101101 11010110 -n(low)- -n(high)
U
SUBTRACT (WORD)
Execute
Time Note
2+r I, X
™
Z380
' M
SER S ANUAL
SUB
5-173