ZiLOG Z80380 User Manual page 61

Z
ILOG
AND [A,]src
← A AND src
Operation: A
A logical AND operation is performed between the corresponding bits of the source operand
and the accumulator and the result is stored in the accumulator. A 1 is stored wherever the
corresponding bits in the two operands are both 1s; otherwise a 0 is stored. The contents
of the source are unaffected.
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if all bits of the result are zero; cleared otherwise
H: Set
P: Set if the parity is even; cleared otherwise
N: Cleared
C: Cleared
Addressing
Mode Syntax
R: AND [A,]R
RX: AND [A,]RX
AND [A,]n
IM:
IR: AND [A,](HL)
X: AND [A,](XY+d)
Field Encodings: r: per convention
y: 0 for IX, 1 for IY
w: 0 for high byte, 1 for low byte
DC-8297-03
src = R, RX, IM, IR, X
Instruction Format
10100-r-
11y11101 1010010w
11100110 ——n—
10100110
11y11101 10100110——d—
AND (BYTE)
Execute
Time Note
2
2
2
2+r
4+r I
™
Z380
U ' M
SER S ANUAL
AND
5-27