ZiLOG Z80380 User Manual page 205

Z
ILOG
SRLW dst
← dst
Operation: tmp
← dst(0)
C
dst(15) ← 0
dst(n) ← tmp(n+1) for n = 0 to 14
The contents of the destination operand are shifted right one bit position. Bit 0 of the
destination operand is moved to the Carry flag and zero is shifted into the most significant
bit of the destination.
Flags: S: Cleared
Z: Set if the result is zero; cleared otherwise
H: Cleared
P: Set if parity of the result is even; cleared otherwise
N: Cleared
C: Set if the bit shifted from bit 0 was a 1; cleared otherwise
Addressing
Mode Syntax
R: SRLW R
RX: SRLW RX
IR: SRLW (HL)
X: SRLW (XY+d)
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y: 0 for IX, 1 for IY
DC-8297-03
dst = R, RX, IR, X
Instruction Format
11101101 11001011 001110rr
11101101 11001011 0011110y
11101101 11001011 00111010
11y11101 11001011 ——d— 00111010
SHIFT RIGHT LOGICAL (WORD)
Execute
Time
2
2
2+r
4+r
™
Z380
U ' M
SER S ANUAL
SRLW
Note
I
5-171