ZiLOG Z80380 User Manual page 44

Z
ILOG
5.5.5 16-Bit Arithmetic Operation
This group of instructions (Table 5-10) provide 16-bit
arithmetic instructions. The Add, Add with Carry, Subtract,
Subtract with Carry, AND, OR, Exclusive OR, and Com-
pare takes one input operand from an addressing register
and the other from a 16-bit register, or from the instruction
itself; the result is returned to the addressing register. The
16-bit Increment and Decrement instructions operate on
data found in a register or in memory; the Indirect Register
or Direct Address addressing mode can be used to
specify the memory operand.
The remaining 16-bit instructions provide general arith-
metic capability using the HL register as one of the input
operands. The word Add, Subtract, Compare, and signed
and unsigned Multiply instructions take one input operand
from the HL register and the other from a 16-bit register,
from the instruction itself, or from memory using Indexed
Instruction Name
Add With Carry (Word)
Add (Word)
Add to Stack Pointer
AND Word
Complement Accumulator
Compare (Word)
Decrement (Word)
Divide Unsigned
Extend Sign (Word)
Increment (Word)
Multiply Word Signed
Multiply Word Unsigned
Negate Accumulator
OR Word
Subtract with Carry (Word)
Subtract (Word)
Subtract from Stack Pointer SUB SP,nn
Exclusive OR
Note: that the instructions with "X" at the rightmost column is affected by
Extended mode. These operate across all the 32 bits in Modulo 2
address calculation.
5-10
Table 5-10. 16-Bit Arithmetic Operation
src/
Format dst
ADC HL,src src
ADCW [HL],src src
ADD HL,src src
ADD IX,src src
ADD IY,src src
ADDW [HL,]src src
ADD SP,nn src
ANDW [HL,]src src
CPLW [HL] dst
CPW [HL,]src src
DEC[W] dst dst
DIVUW [HL,]src src
EXTSW [HL] dst
INC[W] dst dst
MULT [HL,]src src
MULTUW [HL,]src src
NEGW [A] dst
ORW [HL,]src src
SBC HL,src src
SBCW [HL],src src
SUB HL,(nn) src
SUBW [HL,]src src
src
XORW [HL,]src src
32
for
or Direct Address addressing mode. The 32-bit result of a
multiply is returned to the HLz and HL (HL31-HL0). The
unsigned divide instruction takes a 16-bit dividend from
the HL register and a 16-bit divisor from a register, from the
instruction, or memory using the Indexed mode. The 16-bit
quotient is returned in the HL register and the 16-bit
reminder is returned to the HLz (HL31-HL16). The Extend
Sign instruction takes the contents of the HL register and
delivers the 32-bit result to the HLz and HL registers. The
Negate HL instruction negates the contents of the HL
register.
Except for Increment, Decrement, and Extend Sign, all the
instructions in this group set the CPU flags to reflect the
computed result.
BC DE HL SP IX
√ √ √ √
√ √ √ √
√ √ √ √
√ √ √ √
√ √ √
√ √ √ √
√ √ √ √
√
√ √ √ √
√ √ √ √ √
√ √ √ √
√
√ √ √ √ √
√ √ √ √
√ √ √ √
√
√ √ √ √
√ √ √ √
√ √ √ √
√ √ √ √
√ √ √ √
U '
SER
IY nn (nn) (IX+d) (IY+d)
√ √ √ √
√
√
√ √ √ √
√
√ √ √ √
√ √ √ √
√
√ √ √ √
√
√ √ √ √
√ √ √ √
√ √ √ √
√
√ √ √ √
√
√ √ √ √
√
√ √ √ √
DC-8297-03
Z380 ™
M
S ANUAL
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