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Z
ILOG
5.5.6 8-Bit Manipulation, Rotate and Shift
Group
Instructions in this group (Table 5-11) test, set, and reset
bits within bytes, and rotate and shift byte data one bit
position. Bits to be manipulated are specified by a field
within the instruction. Rotate can optionally concatenate
the Carry flag to the byte to be manipulated. Both left and
right shifting is supported. Right shifts can either shift 0 into
bit 7 (logical shifts), or can replicate the sign in bits 6 and
7 (arithmetic shifts). All these instructions, Set Bit and
Reset Bit, set the CPU flags according to the calculated
result; the operand can be a register or a memory location
Instruction Name
Bit Test
Reset Bit
Rotate Left
Rotate Left Accumulator
Rotate Left Circular
Rotate Left Circular (Accumulator)
Rotate Left Digit
Rotate Right
Rotate Right Accumulator
Rotate Right Circular
Rotate Right Circular (Accumulator)
Rotate Right Digit
Set Bit
Shift Left Arithmetic
Shift Right Arithmetic
Shift Right Logical
5.5.7 16-Bit Manipulation, Rotate and Shift
Group
Instructions in this group (Table 5-12) rotate and shift word
data one bit position. Rotate can optionally concatenate
the Carry flag to the word to be manipulated. Both left and
right shifting is supported. Right shifts can either shift 0 into
Instruction Name
Rotate Left Word
Rotate Left Circular Word
Rotate Right Word
Rotate Right Circular Word
Shift Left Arithmetic Word
Shift Right Arithmetic Word
Shift Right Logical Word
DC-8297-03
Table 5-11. Bit Set/Reset/Test, Rotate and Shift Group
Format
BIT dst
RES dst
RL dst
RLA
RLC dst
RLCA
RLD
RR dst
RRA
RRC dst
RRCA
RRD
SET dst
SLA dst
SRA dst
SRL
Table 5-12. 16-Bit Rotate and Shift Group.
Format
BC
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RLW dst
√
RLCW dst
√
RRW dst
√
RRCW dst
√
SLAW dst
√
SRAW dst
√
SRLW
specified by the Indirect Register or Indexed addressing
mode.
The RLD and RRD instructions are provided for manipulat-
ing strings of BCD digits; these rotate 4-bit quantities in
memory specified by the Indirect Register. The low-order
four bits of the accumulator are used as a link between
rotation of successive bytes.
A
B
C
D
E
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bit 15 (logical shifts), or can replicate the sign in bits 14 and
15 (arithmetic shifts). The operand can be a register pair or
memory location specified by the Indirect Register or
Indexed addressing mode, as shown below.
Destination
DE
HL
IX
IY
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SER
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(HL) (HL) (IX+d) (IY+d)
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Z380
'
M
S
ANUAL
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5-11
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