ZiLOG Z80380 User Manual page 131

Z
ILOG
LDDW
Operation: if (LW) then begin
(DE)
(DE+1)
(DE+2)
(DE+3)
DE
HL
BC(15-0)
end
else begin
(DE)
(DE+1)
DE
HL
BC(15-0)
end
This instruction is used for block transfers of words of data. The word of data at the location
addressed by the HL register is loaded into the location addressed by the DE register. Both
the DE and HL registers are then decremented by two or four, thus moving the pointers to
the preceeding words in the array. The BC register, used as a byte counter, is then
decremented by two or four.
Both DE and HL should be even, to allow word transfers on the bus. BC must be even,
transferring an even number of bytes, or the operation is undefined.
Flags: S: Unaffected
Z: Unaffected
H: Cleared
V: Set if the result of decrementing BC is not equal to zero; cleared otherwise
N: Cleared
C: Unaffected
Addressing
Mode Syntax
LDDW
DC-8297-03
←
(HL)
←
(HL+1)
←
(HL+2)
←
(HL+3)
←
DE – 4
←
HL – 4
←
BC(15-0) – 4
←
(HL)
←
(HL+1)
←
DE – 2
←
HL – 2
←
BC(15-0) – 2
Instruction Format
11101101 11101000
LOAD AND DECREMENT (WORD)
Execute
Time
3+r+w
™
Z380
U ' M
SER S ANUAL
LDDW
Note
L
5-97