ZiLOG Z80380 User Manual page 202

Z
ILOG
SRA
SHIFT RIGHT ARITHMETIC (BYTE)
SRA dst
← dst
Operation: tmp
← dst(0)
C
dst(7) ← tmp(7)
dst(n) ← tmp(n+1) for n = 0 to 6
The contents of the destination operand are shifted right one bit position. Bit 0 of the
destination operand is moved to the Carry flag and bit 7 remains unchanged.
Flags: S: Set if the result is negative; cleared otherwise
Z: Set if the result is zero; cleared otherwise
H: Cleared
P: Set if parity of the result is even; cleared otherwise
N: Cleared
C: Set if the bit shifted from bit 0 was a 1; cleared otherwise
Addressing
Mode Syntax
SRA R
R:
IR: SRA (HL)
X: SRA (XY+d)
Field Encodings: r: per convention
y: 0 for IX, 1 for IY
5-168
dst = R, IR, X
Instruction Format
11001011 00101-r-
11001011 00101110
11y11101 11001011 ——d— 00101110
U '
SER
Execute
Time Note
2
2+r
4+r I
DC-8297-03
Z380 ™
M
S ANUAL