ZiLOG Z80380 User Manual page 23

Z
ILOG
3.1 INTRODUCTION
™
The Z380 CPU architecture allows access to 4 Gbytes
32
(2 ) of memory addressing space, and 4G locations of
I/O. It offers 16/32-bit manipulation capability while main-
taining object-code compatibility with the Z80 CPU. In
order to implement these capabilities and new instruction
sets, it has two modes of operation for address manipula-
tion (Native or Extended mode), two modes of operation for
data manipulation (Word or Long Word mode), and a
special set of new Decoder Directives.
On Reset, the Z380 CPU defaults in Native mode and Word
mode. In this condition, it behaves exactly the same as the
Z80 CPU, even though it has access to the entire 4 Gbytes
of memory for data access and 4G locations of I/O space,
For the instructions which work with the DDIR instructions, refer to Appendix D and E.
DC-8297-03
Word
Long Word
Figure 3-1. Z380
U 's M
SER ANUAL
C
HAPTER
N E
ATIVE XTENDED
W M
ORD ODE
D
AND ECODER
access to the newly added registers which includes Ex-
tended registers and register banks, and the capability of
executing all the Z380 instructions.
As described below, the Z380 CPU can be switched
between Word mode and Long Word mode during opera-
tion through the SETC LW and RESC LW instructions, or
Decoder Directives. The Native and Extended modes are
a key exception— it defaults up in Native mode, and can
be set to Extended mode by the instruction. Only Reset can
return it to Native mode. Figure 3-1 illustrates the relation-
ship between these modes of operation.
Native
Z80 Native Mode
™
CPU Operation Modes
3
M , W
ODE ORD
O O
F PERATIONS
D
IRECTIONS
Z380
Extended
™
Z380
U ' M
SER S ANUAL
/L
ONG
3-1