ZiLOG Z80380 User Manual page 58

Z
ILOG
ADD
ADD (WORD)
ADD dst,src
Operation: If (XM) then begin
dst(31-0)
end
else begin
dst(15-0)
end
The source operand is added to the destination and the sum is stored in the destination. The
contents of the source are unaffected. Two's complement addition is performed. Note that
the length of the operand is controlled by the Extended/Native mode selection, which is
consistent with the manipulation of an address by the instruction.
Flags: S: Unaffected
Z: Unaffected
H: Set if there is a carry from bit 11 of the result; cleared otherwise
V: Unaffected
N: Cleared
C: Set if there is a carry from the most significant bit of the result; cleared otherwise
Addressing
Mode Syntax
R: ADD HL,R
RX: ADD XY,R
DA: ADD HL,(nn)
Field Encodings: rr: 00 for BC, 01 for DE, 10 for register to itself, 11 for SP
y: 0 for IX, 1 for IY
5-24
dst = HL; src = BC, DE, HL, SP, DA
or
dst = IX; src = BC, DE, IX, SP
or
dst = IY; src = BC, DE, IY, SP
← dst(31-0) + src(31-0)
← dst(15-0) + src(15-0)
Instruction Format
00rr1001
11y11101 00rr1001
11101101 11000110 -n(low)-
Execute
Time
2
2
n(high)- 2+r
Z380 ™
U ' M
SER S ANUAL
Note
X
X
I, X
DC-8297-03