ZiLOG Z80380 User Manual page 209

Z
ILOG
SUBW [HL,]src
Operation: HL(15-0)
The source operand is subtracted from the HL register and the difference is stored in the
HL register. The contents of the source are unaffected. Two's complement subtraction is
performed.
Flags: S: Set if the result is negative; cleared otherwise
Z: Set if the result is zero; cleared otherwise
H: Set if there is a borrow from bit 12 of the result; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the operands are of different signs and the
result is of the same sign as the source; cleared otherwise
N: Set
C: Set if there is a borrow from the most significant bit of the result; cleared otherwise
Addressing
Mode Syntax
R: SUBW [HL,]R
SUBW [HL,]RX
RX:
IM: SUBW [HL,]nn
X: SUBW [HL,](XY+d)
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y: 0 for IX, 1 for IY
DC-8297-03
src = R, RX, IM, X
← HL(15-0) - src(15-0)
Instruction Format
11101101 100101rr
11y11101 10010111
11101101 10010110 -n(low)- n(high)-
11y11101 11010110 ——d—
U '
SER S
SUBW
SUBTRACT (WORD)
Execute
Time Note
2
2
2
2+r I
™
Z380
M
ANUAL
5-175