ZiLOG Z80380 User Manual page 69

Z
ILOG
CPW [HL,]src
Operation: HL(15-0) – src(15-0)
The source operand is compared with the HL register and the flags are set accordingly. The
contents of the HL register and the source are unaffected. Two's complement subtraction
is performed.
Flags: S: Set if the result is negative; cleared otherwise
Z: Set if the result is zero; cleared otherwise
H: Set if there is a borrow from bit 12 of the result; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the operands are of different signs and the
result is of the same sign as the source; cleared otherwise
N: Set
C: Set if there is a borrow from the most significant bit of the result; cleared otherwise
Addressing
Mode Syntax
R: CPW [HL,]R
RX: CPW [HL,]RX
CPW [HL,]nn
IM:
X: CPW [HL,](XY+d)
Field Encodings: rr:
y:
DC-8297-03
src = R, RX, IM, X
Instruction Format
11101101 101111rr
11y11101 10111111
11101101 10111110 -n(low)- n(high)-
11y11101 11111110 ——d—
00 for BC, 01 for DE, 11 for HL
0 for IX, 1 for IY
Z380
U ' M
SER S ANUAL
CPW
COMPARE (WORD)
Execute
Time Note
2
2
2
4+r I
5-35
™