ZiLOG Z80380 User Manual page 62

Z
ILOG
ANDW
AND (WORD)
ANDW [HL,]src
Operation: HL(15-0)
A logical AND operation is performed between the corresponding bits of the source operand
and the HL register and the result is stored in the HL register. A 1 is stored wherever the
corresponding bits in the two operands are both 1s; otherwise a 0 is stored. The contents
of the source are unaffected.
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if all bits of the result are zero; cleared otherwise
H: Set
P: Set if the parity is even; cleared otherwise
N: Cleared
C: Cleared
Addressing
Mode Syntax
R: ANDW [HL,]R
ANDW [HL,]RX
RX:
IM: ANDW [HL,]nn
X: ANDW [HL,](XY+d)
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y: 0 for IX, 1 for IY
5-28
src = R, RX, IM, X
← HL(15-0) AND src(15-0)
Instruction Format
11101101 101001rr
11y11101 10100111
1110110110100110 n(low)- n(high)-
11y11101 11100110 ——d—
Z380
U ' M
SER S ANUAL
Execute
Time Note
2
2
2
4+r I
DC-8297-03
™