ZiLOG Z80380 User Manual

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Thank you for your interest in the Z380

associated family of products. This Technical Manual describes programming

and operation of the Z380

Z380 Microprocessor Unit (MPU), and products built around Z380

This Z380 User's Manual consists of the following Sections:

™

Z380

Chapter 1 is an introductory section covering the key features and

giving an overview of the architecture of the device.

Address Spaces

Chapter 2 explains the address spaces the Z380 CPU can handle.

Also, this chapter includes a brief description of the on-chip regis-

ters.

Native/Extended Mode, Word/Long Word Mode of Operation,

and Decoder Directives

This chapter provides a detailed explanation on the Z380's unique

features, operation modes, and the Decoder Directives.

Addressing Modes and Data Types

Chapter 4 describes the Addressing mode and data types which the

Z380 can handle.

Instruction Set

Chapter 5 contains an overview of the instruction set; as well as a

detailed instruction-by-instruction description in alphabetical order.

Interrupts and Traps

Chapter 6 explains the interrupts and traps features of the Z380.

Reset

Chapter 7 describes the Reset function.

Z380 Benchmark Appnote

Z380 Questions & Answers

DC-8297-03

Z80380 CPU

SER

™

Superintegration

Architectural Overview

ANUAL

REFACE

™

Central Processing Unit (CPU) and its

™

Core CPU, which is found in the

™

CPU core.

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Summary of Contents for ZiLOG Z80380

Page 1 Z80380 CPU ANUAL REFACE ™ Thank you for your interest in the Z380 Central Processing Unit (CPU) and its associated family of products. This Technical Manual describes programming ™ ™ and operation of the Z380 Superintegration Core CPU, which is found in the Z380 Microprocessor Unit (MPU), and products built around Z380 ™...
Page 2 Also, knowledge of the Z80 ® CPU architecture is desirable. © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 3 ANUAL ILOG ’s M ANUAL HAPTER ™ Z380 RCHITECTURAL VERVIEW 1.1 INTRODUCTION The Z380 CPU incorporates advanced architectural fea- The Z380 CPU, an enhanced version of the Z80 CPU, retains the Z80 CPU instruction set to maintain complete tures that allow fast and efficient throughput and increased binary-code compatiblity with present Z80 and Z180 codes.
Page 4 Z380 ™ ANUAL ILOG 1.1 INTRODUCTION (Continued) 4 Sets of Registers BCz' DEz' HLz' IXz' IXU' IXL' IYz' IYU' IYL' ™ Figure 1-1. Z380 CPU Register Architecture DC-8297-03...
Page 5 Z380 ™ ANUAL ILOG 1.2 CPU ARCHITECTURE The Z380 CPU is a binary-compatible extension of the Z80 will return the Z380 CPU to Native mode. This restriction CPU and the Z180 CPU architecture. High throughput applies because of the possibility of “misplacing” interrupt rates are achieved by a high clock rate, high bus band- service routines or vector tables during the transition from width, and instruction fetch/execute overlap.
Page 6 Z380 ™ ANUAL ILOG 1.2.2 Address Spaces (Continued) 1.2.4. Addressing Modes Each register set includes the primary registers A, F, B, C, Addressing modes are used by the Z380 CPU to calculate D, E, H, L, IX, and IY, as well as the alternate registers A’, the effective address of an operand needed for execution F’, B’, C’, D’, E’, H’, L’, IX’, and IY’.
Page 7 Z380 ™ ANUAL ILOG are handled by a newly added interrupt handing mode, The first three modes are compatible with Z80 interrupt “Assigned Vectored Mode,” which is a fixed vectored modes; the fourth mode provides more flexibility. interrupt mode similar in interrupt handling to the Z180’s interrupts from on-chip peripherals.
Page 8 The benefits of this products to be developed around this CPU core. © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 9 ™ Z380 ANUAL ILOG ’s M ANUAL HAPTER DDRESS PACES 2.1 INTRODUCTION The Z380 CPU supports five address spaces correspond- External I/O Address Space. This consists of all ing to the different types of locations that can be ad- external I/O ports addresses through which peripheral dressed and the method by which the logical addresses devices are accessed.
Page 10 Z380 ™ ANUAL ILOG 2.2 CPU REGISTER SPACE (Continued) 4 Sets of Registers BCz' DEz' HLz' IXz' IXU' IXL' IYz' IYU' IYL' Figure 2-1. Register File Organization (Z380 MPU) DC-8297-03...
Page 11 Z380 ™ ANUAL ILOG 2.2.1 Primary and Working Registers The working register set is divided into two register files: for the IX and IX’ registers, and IYU, IYU’, IYL, and IYL’ for the primary file and the alternate file (designated by prime the IY and IY’...
Page 12 Z380 ™ ANUAL ILOG 2.2.6 Stack Pointer (Continued) Increment/decrement of the Stack Pointer is affected by SP holds 00010000H in Native mode, and 00020000H in modes of operation (Native or Extended). In Native mode, Extended mode. In either case, SPz can be programmed the stack operates in modulo 2 , and in Extended mode, to set Stack frame.
Page 13 Z380 ™ ANUAL ILOG Bits within a byte: 16-bit word at address n: Least Significant Byte Address n Most Significant Byte Address n+1 32-bit word at address n: D7-0 (Least Significant Byte) Address n D15-8 Address n+1 D23-16 Address n+2 D31-24 (Most Significant Byte) Address n+3 Memory addresses:...
Page 14 Z380 ™ ANUAL ILOG 2.5. EXTERNAL I/O ADDRESS SPACE External I/O address space is 4 Gbytes in size and External can take a variety of forms, as shown in Table 2.1. An I/O addresses are generated by I/O instructions except external I/O read or write is always one transaction, regard- those reserved for on-chip I/O address space accesses.
Page 15 ™ ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 16 ™ Z380 ANUAL ILOG ’s M ANUAL HAPTER DDRESS PACES 2.1 INTRODUCTION The Z380 CPU supports five address spaces correspond- External I/O Address Space. This consists of all ing to the different types of locations that can be ad- external I/O ports addresses through which peripheral dressed and the method by which the logical addresses devices are accessed.
Page 17 Z380 ™ ANUAL ILOG 2.2 CPU REGISTER SPACE (Continued) 4 Sets of Registers BCz' DEz' HLz' IXz' IXU' IXL' IYz' IYU' IYL' Figure 2-1. Register File Organization (Z380 MPU) DC-8297-03...
Page 18 Z380 ™ ANUAL ILOG 2.2.1 Primary and Working Registers The working register set is divided into two register files: for the IX and IX’ registers, and IYU, IYU’, IYL, and IYL’ for the primary file and the alternate file (designated by prime the IY and IY’...
Page 19 Z380 ™ ANUAL ILOG 2.2.6 Stack Pointer (Continued) Increment/decrement of the Stack Pointer is affected by SP holds 00010000H in Native mode, and 00020000H in modes of operation (Native or Extended). In Native mode, Extended mode. In either case, SPz can be programmed the stack operates in modulo 2 , and in Extended mode, to set Stack frame.
Page 20 Z380 ™ ANUAL ILOG Bits within a byte: 16-bit word at address n: Least Significant Byte Address n Most Significant Byte Address n+1 32-bit word at address n: D7-0 (Least Significant Byte) Address n D15-8 Address n+1 D23-16 Address n+2 D31-24 (Most Significant Byte) Address n+3 Memory addresses:...
Page 21 Z380 ™ ANUAL ILOG 2.5. EXTERNAL I/O ADDRESS SPACE External I/O address space is 4 Gbytes in size and External can take a variety of forms, as shown in Table 2.1. An I/O addresses are generated by I/O instructions except external I/O read or write is always one transaction, regard- those reserved for on-chip I/O address space accesses.
Page 22 ™ ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 23 ™ Z380 ANUAL ILOG ’s M ANUAL HAPTER ATIVE XTENDED PERATIONS ECODER IRECTIONS 3.1 INTRODUCTION ™ The Z380 CPU architecture allows access to 4 Gbytes access to the newly added registers which includes Ex- ) of memory addressing space, and 4G locations of tended registers and register banks, and the capability of I/O.
Page 24 Z380 ™ ANUAL ILOG 3.2 DECODER DIRECTIVES The Decoder Directive is not an instruction, but rather a The IB decoder directive causes the decoder to fetch an directive to the instruction decoder. The instruction de- additional byte immediately after the existing immediate coder may be directed to fetch an additional byte or word data or direct address, and in front of any trailing opcode of immediate data or address with the instruction, as well...
Page 25 BC, (HL) Loads BC31-BC0 from the locations (HL) to (HL+3). © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 26 Z380 ™ ANUAL ILOG ’s M ANUAL HAPTER DDRESSING ODES AND YPES 4.1 INSTRUCTION an instruction are called addressing modes. The Z380 An instruction is a consecutive list of one or more bytes in CPU supports seven addressing modes; Register, Imme- memory.
Page 27 Z380 ™ ANUAL ILOG 4.2.2 Immediate (IM) (Continued) Instruction 2. Load 24-bit immediate value into OPERATION register OPERAND DDIR IB, LW ;next instruction is in Long Word mode, with ;an additional The operand value is in the instruction immediate data LD HL, 123456H ;load HLz, and HL with constant Immediate mode is often used to initialize registers.
Page 28 ™ Z380 ANUAL ILOG 4.2.4 Direct Address (DA) Depending on the instruction, the operand specified by DA mode is either in the I/O address space (I/O instruction) When Direct Address mode is used, the data processed is or memory address space (all other instructions). at the location whose memory or I/O port address is in the instruction.
Page 29 Z380 ™ ANUAL ILOG 4.2.5 Indexed (X) When the Indexed addressing mode is used, the data The offset portion can be expanded to 16 or 24 bits, processed is at the location whose address is the contents instead of eight bits by using DDIR Immediate Data Direc- of IX or IY in use, offset by an 8-bit signed displacement in tives (DDIR IB for 16-bit offset, DDIR IW for 24-bit offset).
Page 30 ™ Z380 ANUAL ILOG Load accumulator from location (IX-1) in Extended mode SETC ;Set Extended mode A, (IX-1) ;Load into the accumulator the ;contents of the memory location ;whose address is one less than ;the contents of IX Before instruction execution 0001 0000 After instruction execution...
Page 31 Z380 ™ ANUAL ILOG 4.2.6 Program Counter Relative Mode (RA) (Continued) Before instruction execution 0000 1000 After instruction execution 0000 0FFE Address calculation: In Native mode, –2 is encoded as 1000 0FEH in the instruction, and it is sign extended to a 16-bit FFFE value before added to the Program Counter.
Page 32 ™ Z380 ANUAL ILOG 4.2.7 Stack Pointer Relative Mode (SR) Note that computation of the effective address is affected by the operation mode (Native or Extended). In Native For Stack Pointer Relative addressing mode, the data mode, address computation is done in modulo 2 , mean- processed is at the location whose address is the contents ing computation is done in 16-bit and does not affect upper...
Page 33 Z380 ™ ANUAL ILOG 4.2.7 Stack Pointer Relative Mode (SR) (Continued) 2. Load HL from location (SP – 4) in Extended mode, Long Word mode SETC ;In Extended mode DDIR LW ;operate next instruction in Long Word mode LD HL, (SP–4) ;Load into the HL from the ;contents of the memory location ;whose address is four less than...
Page 34 (see Figure 2-2). Bits within byte registers or memory locations can be tested, set, or cleared. © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo-...
Page 35 Z380 ™ ANUAL ILOG ’s M ANUAL HAPTER NSTRUCTION 5.1 INTRODUCTION ™ The Z380 CPU instruction set is a superset of the Z80 CPU Program Control Group and the Z180 MPU; the Z380 CPU is opcode compatible with the Z80 CPU/Z180 MPU. Thus, a Z80/Z180 program Input and Output Operations for External I/O Space can be executed on a Z380 CPU without modification.
Page 36 Z380 ™ ANUAL ILOG 5.2.1 Carry Flag (C) During Load Accumulator with I or R register instruction, the P/V flag is loaded with the IEF2 flag. For details on this The Carry flag is set or cleared depending on the operation topic,.refer to Chapter 6, “Interrupts and Traps.”...
Page 37 ™ Z380 ANUAL ILOG 5.2.7 Condition Codes Table 5-1 lists the condition code mnemonic, the flag setting it represents, and the binary encoding for each The Carry, Zero, Sign, and Parity/Overflow flags are used condition code. to control the operation of the conditional instructions. The operation of these instructions is a function of the state of one of the flags.
Page 38 Z380 ™ ANUAL ILOG 5.3 SELECT REGISTER The Select Register (SR) controls the register set selection compatibility. Access to this register is done by using the and the operating modes of the Z380 CPU. The reserved newly added LDCTL instruction. Also, some of the instruc- bits in the SR are for future expansion;...
Page 39 ™ Z380 ANUAL ILOG 5.3.8. Long Word Mode (LW) 5.3.11. Lock (LCK) This bit controls the Long Word/Word mode selection for This bit controls the Lock/Unlock status of the Z380 CPU. the Z380 CPU. This bit is set by the SETC LW instruction This bit is set by the SETC LCK instruction and cleared by and cleared by the RESC LW instruction.
Page 40 Z380 ™ ANUAL ILOG 5.5 INSTRUCTION SET FUNCTIONAL GROUPS This section presents an overview of the Z380 instruction An Exchange instruction is available for swapping the set, arranged by functional groups. (See Section 5.5 for an contents of the accumulator with another register or with explanation of the notation used in Tables 5-2 through 5- memory, as well as between registers.
Page 41 ™ Z380 ANUAL ILOG 5.5.2 16-Bit and 32-Bit Load, Exchange, SWAP, and PUSH/POP Group This group of load, exchange, and PUSH/POP instructions PUSH/POP instructions are used to save/restore the con- (Table 5-4) allows one or two words of data (two bytes tents of a register onto the stack.
Page 42 Z380 ™ ANUAL ILOG 5.5.2 16-Bit and 32-Bit Load, Exchange, SWAP and PUSH/POP Group (Continued) Table 5-6. Supported Source and Destination Combination for 16-Bit and 32-Bit Load Instructions. Source Destination (nn) (BC) (DE) (HL) (IX+d) (IY+d) (SP+d) (BC) (DE) (HL) (nn) (IX+d) (IY+d)
Page 43 ™ Z380 ANUAL ILOG 5.5.4 8-bit Arithmetic and Logical Group has to be an even number (D0 = 0) in Word mode transfer, and a multiple of four in Long Word mode (D1 and D0 are both 0). Also, in Word or Long Word Block transfer, This group of instructions (Table 5-9) perform 8-bit arith- memory pointer values are recommended to be even metic and logical operations.
Page 44 Z380 ™ ANUAL ILOG 5.5.5 16-Bit Arithmetic Operation This group of instructions (Table 5-10) provide 16-bit or Direct Address addressing mode. The 32-bit result of a arithmetic instructions. The Add, Add with Carry, Subtract, multiply is returned to the HLz and HL (HL31-HL0). The Subtract with Carry, AND, OR, Exclusive OR, and Com- unsigned divide instruction takes a 16-bit dividend from pare takes one input operand from an addressing register...
Page 45 ™ Z380 ANUAL ILOG 5.5.6 8-Bit Manipulation, Rotate and Shift Group Instructions in this group (Table 5-11) test, set, and reset specified by the Indirect Register or Indexed addressing bits within bytes, and rotate and shift byte data one bit mode.
Page 46 Z380 ™ ANUAL ILOG 5.5.8 Program Control Group into the PC. The use of a procedure address stack in this manner allows straightforward implementation of nested This group of instructions (Table 5-13) affect the Program and recursive procedures. Call, Jump, and Jump Relative Counter (PC) and thereby control program flow.
Page 47 ™ Z380 ANUAL ILOG 5.5.9 External Input/Output Instruction the contents of C, E, or L appear D15-D7. These instruc- Group tions do not affect the CPU flags. This group of instructions (Table 5-14) are used for trans- Also, there are I/O instructions available which allow to ferring a byte, a word, or string of bytes or words between specify 16-bit absolute I/O address (with DDIR decoder peripheral devices and the CPU registers or memory.
Page 48 Z380 ™ ANUAL ILOG 5.5.9 External Input/Output Instruction Group (Continued) Table 5-14. External I/O Group Instructions. Instruction Name Format Input IN dst,(C) dst=A, B, C, D, E, H or L Input Accumulator IN A,(n) Input to Word-Wide Register INW dst,(C) dst=BC, DE or HL Input Byte from Absolute Address INAW A,(nn)
Page 49 ™ Z380 ANUAL ILOG 5.5.10 Internal I/O Instruction Group This group (Table 5-15) of instructions is used to access tion in the instruction with Direct Address (IN0 (n)), do not on-chip I/O addressing space on the Z380 CPU. This affect the CPU register, but alters flags accordingly. An- group consists of instructions for transferring a byte from/ other variant, the TSTIO instruction, does a logical AND to to Internal I/O locations and the CPU registers or memory,...
Page 50 Z380 ™ ANUAL ILOG 5.5.11 CPU Control Group into a flag register. For example, this instruction is useful to implement the recursive program, which uses the alter- The instructions in this group (Table 5-16) act upon the nate bank to save a register for the first time, and saves CPU control and status registers or perform other functions registers into memory thereafter.
Page 51 ™ Z380 ANUAL ILOG 5.5.12 Decoder Directives Table 5-17. Decoder Directive Instructions DDIR W Word Mode The Decoder Directives (Table 5-17) are a special instruc- DDIR IB,W Immediate Byte, Word Mode tions to expand the Z80 instruction set to handle the Z380’s DDIR IW,W Immediate Word, Word Mode 4 Gbytes of linear memory addressing space.
Page 52 Z380 ™ ANUAL ILOG 5.6 NOTATION AND BINARY ENCODING (Continued) Condition Codes. The following symbols describe the On the bottom of the each instruction, there are the field condition codes. encodings, if applicable. For the cases which call out “per convention,”...
Page 53 ™ Z380 ANUAL ILOG Table 5-18. Execution Time Operation Byte Word Word Long Long Long Long Long Sequence W/B/B B/W/B B/B/W B/B/B/B Memory Read 9-10 Memory Write Internal I/O Read Internal I/O Write 1X External I/O Read 1X External I/O Write 2X External I/O Read 9-11 9-11...
Page 54 Z380 ™ ANUAL ILOG ADD WITH CARRY (BYTE) ADC A,src src = R, RX, IM, IR, X ← A + src + C Operation: The source operand together with the Carry flag is added to the accumulator and the sum is stored in the accumulator.
Page 55 ™ Z380 ANUAL ILOG ADD WITH CARRY (WORD) ADC HL,src dst = HL src = BC, DE, HL, SP ← HL(15-0) + src(15-0) + C Operation: HL(15-0) The source operand together with the Carry flag is added to the HL register and the sum is stored in the HL register.
Page 56 Z380 ™ ANUAL ILOG ADCW ADD WITH CARRY (WORD) ADCW [HL,]src src = R, RX, IM, X ← HL(15-0) + src(15-0) + C Operation: HL(15-0) The source operand together with the Carry flag is added to the HL register and the sum is stored in the HL register.
Page 57 ™ Z380 ANUAL ILOG ADD (BYTE) ADD A,src src = R, RX, IM, IR, X ← A + src Operation: The source operand is added to the accumulator and the sum is stored in the accumulator. The contents of the source are unaffected. Two’s complement addition is performed. Flags: Set if the result is negative;...
Page 58 Z380 ™ ANUAL ILOG ADD (WORD) ADD dst,src dst = HL; src = BC, DE, HL, SP, DA dst = IX; src = BC, DE, IX, SP dst = IY; src = BC, DE, IY, SP Operation: If (XM) then begin ←...
Page 59 ™ Z380 ANUAL ILOG ADD TO STACK POINTER (WORD) ADD SP,src src = IM Operation: if (XM) then begin ← SP(31-0) SP(31-0) + src(31-0) else begin ← SP(15-0) SP(15-0) + src(15-0) The source operand is added to the SP register and the sum is stored in the SP register. This has the effect of allocating or allocating space on the stack.
Page 60 Z380 ™ ANUAL ILOG ADDW ADD (WORD) ADDW [HL,]src src = R, RX, IM, X ← HL(15-0) + src(15-0) Operation: HL(15-0) The source operand is added to the HL register and the sum is stored in the HL register. The contents of the source are unaffected.
Page 61 ™ Z380 ANUAL ILOG AND (BYTE) AND [A,]src src = R, RX, IM, IR, X ← A AND src Operation: A logical AND operation is performed between the corresponding bits of the source operand and the accumulator and the result is stored in the accumulator. A 1 is stored wherever the corresponding bits in the two operands are both 1s;...
Page 62 Z380 ™ ANUAL ILOG ANDW AND (WORD) ANDW [HL,]src src = R, RX, IM, X ← HL(15-0) AND src(15-0) Operation: HL(15-0) A logical AND operation is performed between the corresponding bits of the source operand and the HL register and the result is stored in the HL register. A 1 is stored wherever the corresponding bits in the two operands are both 1s;...
Page 63 ™ Z380 ANUAL ILOG BIT TEST BIT b,dst dst = R, IR, X ← NOT dst(b) Operation: The specified bit b within the destination operand is tested, and the Zero flag is set to 1 if the specified bit is 0, otherwise the Zero flag is cleared to 0. The contents of the destination are unaffected.
Page 64 Z380 ™ ANUAL ILOG BTEST BANK TEST BTEST ← SR(16) Operation: ← SR(24) ← SR(0) ← SR(8) The Alternate Register bits in the Select Register (SR) are transferred to the flags. This allows the program to determine the state of the machine. Set if the alternate bank IX is in use;...
Page 65 ™ Z380 ANUAL ILOG CALL CALL CALL [cc,]dst dst = DA Operation: if (cc is TRUE) then begin if (XM) then begin ← SP - 4 ← (SP) PC(7-0) ← (SP+1) PC(15-8) ← (SP+2) PC(23-16) ← (SP+3) PC(31-24) ← PC(31-0) dst(31-0) else begin ←...
Page 66 Z380 ™ ANUAL ILOG CALR CALL RELATIVE CALR [cc,]dst dst = RA Operation: if (cc is true) then begin ← SIGN EXTEND dst if (XM) then begin ← SP - 4 ← (SP) PC(7-0) ← (SP+1) PC(15-8) ← (SP+2) PC(23-16) ←...
Page 67 ™ Z380 ANUAL ILOG COMPLEMENT CARRY FLAG ← NOT C Operation: The Carry flag is inverted. Flags: Unaffected Unaffected The previous state of the Carry flag Unaffected Cleared Set if the Carry flag was clear before the operation; cleared otherwise Addressing Execute Mode...
Page 68 Z380 ™ ANUAL ILOG COMPARE (BYTE) CP [A,]src src = R, RX, IM, IR, X Operation: A – src The source operand is compared with the accumulator and the flags are set accordingly. The contents of the accumulator and the source are unaffected. Two’s complement subtraction is performed.
Page 69 ™ Z380 ANUAL ILOG COMPARE (WORD) CPW [HL,]src src = R, RX, IM, X Operation: HL(15-0) – src(15-0) The source operand is compared with the HL register and the flags are set accordingly. The contents of the HL register and the source are unaffected. Two’s complement subtraction is performed.
Page 70 Z380 ™ ANUAL ILOG COMPARE AND DECREMENT (BYTE) Operation: A - (HL) if (XM) then begin ← HL(31-0) HL(31-0) - 1 else begin ← HL(15-0) HL(15-0) - 1 ← BC(15-0) BC(15-0) - 1 This instruction is used for searching strings of byte data. The byte of data at the location addressed by the HL register is compared with the contents of the accumulator and the Sign and Zero flags are set to reflect the result of the comparison.
Page 71 ™ Z380 ANUAL ILOG CPDR COMPARE, DECREMENT AND REPEAT (BYTE) CPDR Operation: Repeat until (BC=0 OR match) begin A - (HL) if (XM) then begin ← HL(31-0) HL(31-0) - 1 else begin ← HL(15-0) HL(15-0) - 1 ← BC(15-0) BC(15-0) - 1 This instruction is used for searching strings of byte data.
Page 72 Z380 ™ ANUAL ILOG COMPARE AND INCREMENT (BYTE) Operation: A - (HL) if (XM) then begin ← HL(31-0) HL(31-0) + 1 else begin ← HL(15-0) HL(15-0) + 1 ← BC(15-0) BC(15-0) - 1 This instruction is used for searching strings of byte data. The byte of data at the location addressed by the HL register is compared with the contents of the accumulator and the Sign and Zero flags are set to reflect the result of the comparison.
Page 73 ™ Z380 ANUAL ILOG CPIR COMPARE, INCREMENT AND REPEAT (BYTE) CPIR Operation: Repeat until (BC=0 OR match) begin A - (HL) if (XM) then begin ← HL(31-0) HL(31-0) + 1 else begin ← HL(15-0) HL(15-0) + 1 ← BC(15-0) BC(15-0) - 1 This instruction is used for searching strings of byte data.
Page 74 Z380 ™ ANUAL ILOG COMPLEMENT ACCUMULATOR CPL [A] ← NOT A Operation: The contents of the accumulator are complemented (one's complement); all 1s are changed to 0 and vice-versa. Flags: Unaffected Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note CPL [A]...
Page 75 ™ Z380 ANUAL ILOG CPLW COMPLEMENT HL REGISTER (WORD) CPLW [HL] ← NOT HL(15-0) Operation: HL(15-0) The contents of the HL register are complemented (ones complement); all 1s are changed to 0 and vice-versa. Flags: Unaffected Unaffected Unaffected Unaffected Addressing Execute Mode Syntax...
Page 76 Z380 ™ ANUAL ILOG DECIMAL ADJUST ACCUMULATOR ← Decimal Adjust A Operation: The accumulator is adjusted to form two 4-bit BCD digits following a binary, two’s complement addition or subtraction on two BCD-encoded bytes. The table below indicates the operation performed for addition (ADD, ADC, INC) or subtraction (SUB, SBC, DEC, NEG).
Page 77 ™ Z380 ANUAL ILOG DDIR DECODER DIRECTIVE DDIR mode mode = W or LW, IB or IW Operation: None, decoder directive only This is not an instruction, but rather a directive to the instruction decoder. The instruction decoder may be directed to fetch an additional byte or word of immediate data or address with the instruction, as well as tagging the instruction for execution in either Word or Long Word mode.
Page 78 Z380 ™ ANUAL ILOG DECREMENT (BYTE) DEC dst dst = R, RX, IR, X dst ← dst – 1 Operation: The destination operand is decremented by one and the result is stored in the destination. Two’s complement subtraction is performed. Flags: Set if the result is negative;...
Page 79 ™ Z380 ANUAL ILOG DEC[W] DECREMENT (WORD) DEC[W] dst dst = R, RX Operation: if (XM) then begin ← dst(31-0) dst(31-0) - 1 else begin ← dst(15-0) dst(15-0) - 1 The destination operand is decremented by one and the result is stored in the destination. Two’s complement subtraction is performed.
Page 80 Z380 ™ ANUAL ILOG DISABLE INTERRUPTS DI [n] Operation: if (n is present) then begin for i=1 to 4 begin if (n(i) = 1) then begin ← IER(i-1) if (n(0) = 1) then begin ← SR(5) else begin ← SR(5) If an argument is present, disable the selected interrupts by clearing the appropriate enable bits in the Interrupt Enable Register, and then clear the Interrupt Enable Flag (IEF1) in the Select Register (SR) if the least-significant bit of the argument is set, disabling maskable...
Page 81 ™ Z380 ANUAL ILOG DIVUW DIVIDE UNSIGNED (WORD) DIVUW [HL,]src src = R, RX, IM, X ← HL / src Operation: HL(15-0) HL(31-16) ← remainder The contents of the the HL register (dividend) are divided by the source operand (divisor) and the quotient is stored in the lower word of the HL register;...
Page 82 Z380 ™ ANUAL ILOG DJNZ DECREMENT AND JUMP IF NON-ZERO DJNZ dst dst = RA ← Operation: If (B <> 0) then begin ← SIGN EXTEND dst if (XM) then begin ← PC(31-0) PC(31-0) + dst(31-0) else begin ← PC(15-0) PC(15-0) + dst(15-0) The B register is decremented by one.
Page 83: Enable Interrupts
™ Z380 ANUAL ILOG ENABLE INTERRUPTS EI [n] Operation: if (n is present) then begin for i=1 to 4 begin if (n(i) = 1) then begin ← IER(i-1) if (n(0) = 1) then begin ← SR(5) else begin ← SR(5) If an argument is present, enable the selected interrupts by setting the appropriate enable bits in the Interrupt Enable Register, and then set the Interrupt Enable Flag (IEF1) in the Select Register (SR) if the least-significant bit of the argument is set, enabling maskable...
Page 84 Z380 ™ ANUAL ILOG EXCHANGE ACCUMULATOR/FLAG WITH ALTERNATE BANK EX AF,AF’ ← NOT SR(0) Operation: SR(0) Bit 0 of the Select Register (SR), which controls the selection of primary or alternate bank for the accumulator and flag register, is complemented, thus effectively exchanging the accumulator and flag registers between the two banks.
Page 85 ™ Z380 ANUAL ILOG EXCHANGE ADDRESSING REGISTER WITH TOP OF STACK EX (SP),dst dst = HL, IX, IY Operation: if (LW) then begin (SP+3) ↔ dst(31-24) (SP+2) ↔ dst(23-16) ↔ dst(15-8) (SP+1) ↔ dst(7-0) (SP) The contents of the destination register are exchanged with the top of the stack. In Long Word mode this exchange is two words;...
Page 86 Z380 ™ ANUAL ILOG EXCHANGE REGISTER (WORD) EX dst,src dst = R, RX src = R, RX Operation: if (LW) then begin ↔ dst(31-0) src(31-0) else begin ↔ dst(15-0) src(15-0) The contents of the destination are exchanged with the contents of the source. Flags: Unaffected Unaffected...
Page 87 ™ Z380 ANUAL ILOG EXCHANGE REGISTER WITH ALTERNATE REGISTER (BYTE) EX dst,src src = R dst ↔ src Operation: The contents of the destination are exchanged with the contents of the source, where the destination is a register in the primary bank and the source is the corresponding register in the alternate bank Flags: Unaffected...
Page 88 Z380 ™ ANUAL ILOG EXCHANGE REGISTER WITH ALTERNATE REGISTER (WORD) EX dst,src src = R, RX Operation: if (LW) then begin ↔ dst(31-0) src(31-0) else begin ↔ dst(15-0) src(15-0) The contents of the destination are exchanged with the contents of the source, where the destination is a word register in the primary bank and the source is the corresponding word register in the alternate bank.
Page 89 ™ Z380 ANUAL ILOG EXCHANGE WITH ACCUMULATOR EX A,src src = R, IR dst ↔ src Operation: The contents of the accumulator are exchanged with the contents of the source. Flags: Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time...
Page 90 Z380 ™ ANUAL ILOG EXALL EXCHANGE ALL REGISTERS WITH ALTERNATE BANK EXALL SR(24) ← NOT SR(24) Operation: SR(16) ← NOT SR(16) ← NOT SR(8) SR(8) Bits 8, 16, and 24 of the Select Register (SR), which control the selection of primary or alternate bank for the BC, DE, HL, IX, and IY registers, are complemented, thus effectively exchanging the BC, DE, HL, IX, and IY registers between the two banks.
Page 91 ™ Z380 ANUAL ILOG EXTS EXTEND SIGN (BYTE) EXTS [A] ← Operation: if (A(7)=0) then begin ¨ if (LW) then begin ← HL(31-16) 0000h else begin ¨ if (LW) then begin ← HL(31-16) FFFFh The contents of the accumulator, considered as a signed, two’s complement integer, are sign-extended to 16 bits and the result is stored in the HL register.
Page 92 Z380 ™ ANUAL ILOG EXTSW EXTEND SIGN (WORD) EXTSW [HL] Operation: If (HL(15)=0) then begin HL(31-16) ← 0000h else begin HL(31-16) ← FFFFh The contents of the low word of the HL register, considered as a signed, two's complement integer, are sign-extended to 32 bits in the HL register. This instruction is useful for conversion of 16-bit signed operands into 32-bit signed operands.
Page 93 ™ Z380 ANUAL ILOG EXCHANGE REGISTERS WITH ALTERNATE BANK ← NOT SR(8) Operation: SR(8) Bit 8 of the Select Register (SR), which controls the selection of primary or alternate bank for the BC, DE, and HL registers, is complemented, thus effectively exchanging the BC, DE, and HL registers between the two banks.
Page 94 Z380 ™ ANUAL ILOG EXXX EXCHANGE IX REGISTER WITH ALTERNATE BANK EXXX SR(16) ← NOT SR(16) Operation: Bit 16 of the Select Register (SR), which controls the selection of primary or alternate bank for the IX register, is complemented, thus effectively exchanging the IX register between the two banks.
Page 95 ™ Z380 ANUAL ILOG EXXY EXCHANGE IY REGISTER WITH ALTERNATE BANK EXXY SR(24) ← NOT SR(24) Operation: Bit 24 of the Select Register (SR), which controls the selection of primary or alternate bank for the IY register, is complemented, thus effectively exchanging the IY register between the two banks.
Page 96 Z380 ™ ANUAL ILOG HALT HALT HALT Operation: CPU Halts The CPU operation is suspended until either an interrupt request or reset request is received. This instruction is used to synchronize the CPU with external events, preserving its state until an interrupt or reset request is accepted. After an interrupt is serviced, the instruction following HALT is executed.
Page 97 ™ Z380 ANUAL ILOG INTERRUPT MODE SELECT IM p p = 0, 1, 2, 3 SR(4-3) ← p Operation: The interrupt mode of operation is set to one of four modes. (See Chapter 6 for a description of the various modes for responding to interrupts). The current interrupt mode can be read from the Select Register (SR).
Page 98 Z380 ™ ANUAL ILOG INPUT (BYTE) IN dst,(C) dst = R dst ← (C) Operation: The byte of data from the selected peripheral is loaded into the destination register. During the I/O transaction, the contents of the 32-bit BC register are placed on the address bus. Flags: Set if the input data is negative;...
Page 99 ™ Z380 ANUAL ILOG INPUT (WORD) INW dst,(C) dst = R ← (C) Operation: dst(15-0) The word of data from the selected peripheral is loaded into the destination register. During the I/O transaction, the contents of the 32-bit BC register are placed on the address bus. Flags: Set if the input data is negative;...
Page 100 Z380 ™ ANUAL ILOG INPUT ACCUMULATOR IN A,(n) ← (n) Operation: The byte of data from the selected peripheral is loaded into the accumulator. During the I/O transaction, the 8-bit peripheral address from the instruction is placed on the low byte of the address bus, the contents of the accumulator are placed on address lines A15-A8, and the high-order address lines are all zeros.
Page 101 ™ Z380 ANUAL ILOG INPUT (FROM PAGE 0) IN0 dst,(n) dst = R dst ← (n) Operation: The byte of data from the selected on-chip peripheral is loaded into the destination register. No external I/O transaction will be generated as a result of this instruction, although the I/O address will appear on the address bus while this internal read is occurring.
Page 102 Z380 ™ ANUAL ILOG INPUT DIRECT FROM PORT ADDRESS (BYTE) INA A,(nn) ← (nn) Operation: The byte of data from the selected peripheral is loaded into the accumulator. During the I/O transaction, the peripheral address from the instruction is placed on the address bus. Any bytes of address not specified in the instruction are driven on the address lines as all zeros.
Page 103 ™ Z380 ANUAL ILOG INAW INPUT DIRECT FROM PORT ADDRESS (WORD) INAW HL,(nn) ← (nn) Operation: HL(15-0) The word of data from the selected peripheral is loaded into the HL register. During the I/O transaction, the peripheral address from the instruction is placed on the address bus. Any bytes of address not specified in the instruction are driven on the address lines as all zeros.
Page 104 Z380 ™ ANUAL ILOG INCREMENT (BYTE) INC dst dst = R, RX, IR, X dst ← dst + 1 Operation: The destination operand is incremented by one and the sum is stored in the destination. Two’s complement addition is performed. Flags: Set if the result is negative;...
Page 105 ™ Z380 ANUAL ILOG INC[W] INCREMENT (WORD) INC[W] dst dst = R, RX Operation: if (XM) then begin < dst(31-0) dst(31-0) + 1 else begin ← dst(15-0) dst(15-0) + 1 The destination operand is incremented by one and the sum is stored in the destination. Two’s complement addition is performed.
Page 106 Z380 ™ ANUAL ILOG INPUT AND DECREMENT (BYTE) ← (C) Operation: (HL) ← B – 1 ← HL – 1 This instruction is used for block input of strings of data. During the I/O transaction the 32- bit BC register is placed on the address bus. Note that the B register contains the loop count for this instruction so that A15-A8 are not useable as part of a fixed port address.
Page 107 ™ Z380 ANUAL ILOG INDW INPUT AND DECREMENT (WORD) INDW ← (DE) Operation: (HL) ← BC(15-0) – 1 BC(15-0) ← HL – 2 This instruction is used for block input of strings of data. During the I/O transaction the 32- bit DE register is placed on the address bus.
Page 108 Z380 ™ ANUAL ILOG INDR INPUT, DECREMENT AND REPEAT (BYTE) INDR Operation: repeat until (B=0) begin ← (C) (HL) ← B – 1 ← HL – 1 This instruction is used for block input of strings of data. The string of input data from the selected peripheral is loaded into memory at consecutive addresses, starting with the location addressed by the HL register and decreasing.
Page 109 ™ Z380 ANUAL ILOG INDRW INPUT, DECREMENT AND REPEAT (WORD) INDRW Operation: repeat until (BC=0) begin ← (HL) (DE) ← BC(15-0) BC(15-0) – 1 ← HL – 2 This instruction is used for block input of strings of data. The string of input data from the selected peripheral is loaded into memory at consecutive addresses, starting with the location addressed by the HL register and decreasing.
Page 110 Z380 ™ ANUAL ILOG INPUT AND INCREMENT (BYTE) ← (C) Operation: (HL) ← B – 1 ← HL + 1 This instruction is used for block input of strings of data. During the I/O transaction the 32- bit BC register is placed on the address bus. Note that the B register contains the loop count for this instruction so that A15-A8 are not useable as part of a fixed port address.
Page 111 ™ Z380 ANUAL ILOG INIW INPUT AND INCREMENT (WORD) INIW ← (DE) Operation: (HL) ← BC(15-0) – 1 BC(15-0) ← HL + 2 This instruction is used for block input of strings of data. During the I/O transaction the 32-bit DE register is placed on the address bus. First the word of data from the selected peripheral is loaded into the memory location addressed by the HL register.
Page 112 Z380 ™ ANUAL ILOG INIR INPUT, INCREMENT AND REPEAT (BYTE) INIR Operation: repeat until (B=0) begin ← (C) (HL) ← B – 1 ← HL + 1 This instruction is used for block input of strings of data. The string of input data from the selected peripheral is loaded into memory at consecutive addresses, starting with the location addressed by the HL register and increasing.
Page 113 ™ Z380 ANUAL ILOG INIRW INPUT, INCREMENT AND REPEAT (WORD) INIRW Operation: repeat until (BC=0) begin ← (HL) (DE) ← BC(15-0) BC(15-0) – 1 ← HL + 2 This instruction is used for block input of strings of data. The string of input data from the selected peripheral is loaded into memory at consecutive addresses, starting with the location addressed by the HL register and increasing.
Page 114 Z380 ™ ANUAL ILOG JUMP JP [cc,]dst dst = IR, DA Operation: if (cc is TRUE) then begin if (XM) then begin ← PC(31-0) dst(31-0) else begin ← PC(15-0) dst(15-0) A conditional jump transfers program control to the destination address if the setting of a selected flag satisfies the condition code “cc”...
Page 115 ™ Z380 ANUAL ILOG JUMP RELATIVE JR [cc,]dst dst = RA Operation: if (cc is TRUE) then begin dst ← SIGN EXTEND dst if (XM) then begin ← PC(31-0) PC(31-0) + dst(31-0) else begin ← PC(15-0) PC(15-0) + dst(15-0) A conditional Jump transfers program control to the destination address if the setting of a selected flag satisfies the condition code “cc”...
Page 116 Z380 ™ ANUAL ILOG LOAD ACCUMULATOR LD dst,src dst = A src = R, RX, IM, IR, DA, X dst = R, RX, IR, DA, X src = A dst ← src Operation: The contents of the source are loaded into the destination. Unaffected Flags: Unaffected...
Page 117 ™ Z380 ANUAL ILOG LOAD IMMEDIATE (BYTE) LD dst,n dst = R, RX, IR, X dst ← n Operation: The byte of immediate data is loaded into the destination. Flags: Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note...
Page 118 Z380 ™ ANUAL ILOG LOAD IMMEDIATE (WORD) LD dst,nn dst = R, RX Operation: if (LW) then begin ← dst(31-0) else begin ← dst(15-0) The word of immediate data is loaded into the destination. Flags: Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Addressing Execute...
Page 119 ™ Z380 ANUAL ILOG LOAD IMMEDIATE (WORD) LDW dst,nn dst = IR Operation: if (LW) then begin ← dst(31-0) else begin ← dst(15-0) The word of immediate data is loaded into the destination. Flags: Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Addressing Execute Mode...
Page 120 Z380 ™ ANUAL ILOG LOAD REGISTER (BYTE) LD dst,src dst = R src = R, RX, IM, IR, X dst = R, RX, IR, X src = R dst ← src Operation: The contents of the source are loaded into the destination. Unaffected Flags: Unaffected...
Page 121 ™ Z380 ANUAL ILOG LD[W] LOAD REGISTER (WORD) LD[W] dst,src dst = R src = R, RX, IR, DA, X, SR dst = R, RX, IR, DA, X, SR src = R Operation: if (LW) then begin ← dst(31-0) src(31-0) else begin ←...
Page 122 Z380 ™ ANUAL ILOG LD[W] LOAD REGISTER (WORD) Load from Register Addressing Execute Mode Syntax Instruction Format Time Note LD RX,R 11y11101 00rr0111 LD IX,IY 11011101 00100111 LD IY,IX 11111101 00100111 LD (IR),RR 11111101 00rr11ri LD (IR),RX 11y11101 00ri0001 LD (nn),HL 00100010 -n(low)- -n(high) I, L LD (nn),R...
Page 123 ™ Z380 ANUAL ILOG LOAD STACK POINTER LD dst,src dst = SP src = R, RX, IM, DA dst = DA src = SP Operation: if (LW) then begin ← dst(31-0) src(31-0) else begin ← dst(15-0) src(15-0) The contents of the source are loaded into the destination. Unaffected Flags: Unaffected...
Page 124 Z380 ™ ANUAL ILOG LOAD FROM I OR R REGISTER (BYTE) LD dst,src dst = A src = I, R dst ← src Operation: The contents of the source are loaded into the accumulator. The contents of the source are not affected.
Page 125 ™ Z380 ANUAL ILOG LOAD INTO I OR R REGISTER (BYTE) LD dst,src dst = I, R src = A dst ← src Operation: The contents of the accumulator are loaded into the destination. Note that the R register does not contain the refresh address and is not modified by refresh transactions.
Page 126 Z380 ™ ANUAL ILOG LD[W] LOAD I REGISTER (WORD) LD[W] dst,src dst = HL src = I dst = I src = HL Operation: if (LW) then begin ← dst(31-0) src(31-0) else begin ← dst(15-0) src(15-0) The contents of the source are loaded into the destination Unaffected Flags: Unaffected...
Page 127 ™ Z380 ANUAL ILOG LDCTL LOAD CONTROL REGISTER (BYTE) LDCTL dst,src dst = DSR, XSR, YSR src = A, IM dst = A src = DSR, XSR, YSR dst = SR src = A, IM Operation: if (dst = SR) then begin SR(31-24) ←...
Page 128 Z380 ™ ANUAL ILOG LDCTL LOAD FROM CONTROL REGISTER (WORD) LDCTL dst,src dst = HL src = SR Operation: if (LW) then begin ← dst(31-0) src(31-0) else begin ← dst(15-0) src(15-0) The contents of the Select Register (SR) are loaded into the HL register. Flags: Unaffected Unaffected...
Page 129 ™ Z380 ANUAL ILOG LDCTL LOAD INTO CONTROL REGISTER (WORD) LDCTL dst,src dst = SR src = HL Operation: if (LW) then begin dst(31-16) ← HL(31-16) else begin dst(31-24) ← HL(15-8) dst(23-16) ← HL(15-8) ← dst(15-8) HL(15-8) ← dst(0) HL(0) The contents of the HL register are loaded into the Select Register (SR).
Page 130 Z380 ™ ANUAL ILOG LOAD AND DECREMENT (BYTE) ← (HL) Operation: (DE) ← DE – 1 ← HL – 1 ← BC(15-0) – 1 BC(15-0) This instruction is used for block transfers of strings of data. The byte of data at the location addressed by the HL register is loaded into the location addressed by the DE register.
Page 131 ™ Z380 ANUAL ILOG LDDW LOAD AND DECREMENT (WORD) LDDW Operation: if (LW) then begin ← (DE) (HL) ← (DE+1) (HL+1) ← (DE+2) (HL+2) ← (DE+3) (HL+3) ← DE – 4 ← HL – 4 ← BC(15-0) BC(15-0) – 4 else begin ←...
Page 132 Z380 ™ ANUAL ILOG LDDR LOAD, DECREMENT AND REPEAT (BYTE) LDDR Operation: repeat until BC=0 begin ← (DE) (HL) ← DE – 1 ← HL – 1 ← BC(15-0) BC(15-0) – 1 This instruction is used for block transfers of strings of data. The bytes of data at the location addressed by the HL register are loaded into memory starting at the location addressed by the DE register.
Page 133 ™ Z380 ANUAL ILOG LDDRW LOAD, DECREMENT AND REPEAT (WORD) LDDRW Operation: repeat until (BC=0) begin if (LW) then begin ← (DE) (HL) ← (DE+1) (HL+1) ← (DE+2) (HL+2) ← (DE+3) (HL+3) ← DE – 4 ← HL – 4 ←...
Page 134 Z380 ™ ANUAL ILOG LOAD AND INCREMENT (BYTE) ← (HL) Operation: (DE) ← DE + 1 ← HL + 1 ← BC(15-0) – 1 BC(15-0) This instruction is used for block transfers of strings of data. The byte of data at the location addressed by the HL register is loaded into the location addressed by the DE register.
Page 135 ™ Z380 ANUAL ILOG LDIW LOAD AND INCREMENT (WORD) LDIW Operation: if (LW) then begin ← (DE) (HL) ← (DE+1) (HL+1) ← (DE+2) (HL+2) ← (DE+3) (HL+3) ← DE + 4 ← HL + 4 ← BC(15-0) BC(15-0) – 4 else begin ←...
Page 136 Z380 ™ ANUAL ILOG LDIR LOAD, INCREMENT AND REPEAT (BYTE) LDIR Operation: repeat until (BC=0) begin ← (DE) (HL) ← DE + 1 ← HL + 1 ← BC(15-0) BC(15-0) – 1 This instruction is used for block transfers of strings of data. The bytes of data at the location addressed by the HL register are loaded into memory starting at the location addressed by the DE register.
Page 137 ™ Z380 ANUAL ILOG LDIRW LOAD, INCREMENT AND REPEAT (WORD) LDIRW Operation: repeat until (BC=0) begin if (LW) then begin ← (DE) (HL) ← (DE+1) (HL+1) ← (DE+2) (HL+2) ← (DE+3) (HL+3) ← DE + 4 ← HL + 4 ←...
Page 138 Z380 ™ ANUAL ILOG MULTIPLY UNSIGNED (BYTE) MLT R src = R R(15-0) ← R(7-0) x R(15-8) Operation: The contents of the upper byte of the source register are multiplied by the contents of the lower byte of the source register and the product is stored in the source register. Both operands.
Page 139 ™ Z380 ANUAL ILOG MTEST MODE TEST MTEST ← SR(7) Operation: ← SR(6) ← SR(1) The three mode control bits in the Select Register (SR) are transferred to the flags. This allows the program to determine the state of the machine. Flags: Set if Extended mode is in effect;...
Page 140 Z380 ™ ANUAL ILOG MULTW MULTIPLY (WORD) MULTW [HL,]src src = R, RX, IM, X ← HL(15-0) x src(15-0) Operation: HL(31-0) The contents of the HL register are multiplied by the source operand and the product is stored in the HL register. The contents of the source are unaffected. Both operands are treated as signed, two’s complement integers.
Page 141 ™ Z380 ANUAL ILOG MULTUW MULTIPLY UNSIGNED (WORD) MULTUW [HL,]src src = R, RX, IM, X ← HL(15-0) x src(15-0) Operation: HL(31-0) The contents of the HL register are multiplied by the source operand and the product is stored in the HL register. The contents of the source are unaffected. Both operands are treated as unsigned, binary integers.
Page 142 Z380 ™ ANUAL ILOG NEGATE ACCUMULATOR NEG [A] ← -A Operation: The contents of the accumulator are negated, that is replaced by its two’s complement value. Note that 80h is replaced by itself, because in two’s complement representation the negative number with the greatest magnitude has no positive counterpart; for this case, the Overflow flag is set to 1.
Page 143 ™ Z380 ANUAL ILOG NEGW NEGATE HL REGISTER (WORD) NEGW [HL] ← -HL(15-0) Operation: HL(15-0) The contents of the HL register are negated, that is replaced by its two’s complement value. Note that 8000h is, replaced by itself, because in two’s complement representation the negative number with the greatest magnitude has no positive counterpart;...
Page 144: Nop No Operation
Z380 ™ ANUAL ILOG NO OPERATION Operation: None No operation. Flags: S: Unaffected Z: Unaffected H: Unaffected V: Unaffected N: Unaffected C: Unaffected Addressing Execute Mode Syntax Instruction Format Time Note 00000000 5-110 DC-8297-03...
Page 145 ™ Z380 ANUAL ILOG OR (BYTE) OR [A,]src src = R, RX, IM, IR, X ← A OR src Operation: A logical OR operation is performed between the corresponding bits of the source operand and the accumulator and the result is stored in the accumulator. A 1 bit is stored wherever either of the corresponding bits in the two operands is 1;...
Page 146 Z380 ™ ANUAL ILOG OR (WORD) ORW [HL,]src src = R, RX, IM, X ← HL(15-0) OR src(15-0) Operation: HL(15-0) A logical OR operation is performed between the corresponding bits of the source operand and the HL register and the result is stored in the HL register. A 1 bit is stored wherever either of the corresponding bits in the two operands is 1;...
Page 147 ™ Z380 ANUAL ILOG OTDM OUTPUT DECREMENT MEMORY OTDM (C) ← (HL) Operation: ← C – 1 ← B – 1 HL ← HL – 1 This instruction is used for block output of strings of data to on-chip peripherals. No external I/O transaction will be generated as a result of this instruction, although the I/O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring.
Page 148 Z380 ™ ANUAL ILOG OTDMR OUTPUT, DECREMENT MEMORY REPEAT OTDMR Operation: repeat until (B=0) begin (C) ← (HL) ← C – 1 ← B – 1 HL ← HL – 1 This instruction is used for block output of strings of data to on-chip peripherals. No external I/O transaction will be generated as a result of this instruction, although the I/O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring.
Page 149 ™ Z380 ANUAL ILOG OTDR OUTPUT, DECREMENT AND REPEAT (BYTE) OTDR Operation: repeat until (B=0) begin ← B – 1 (C) ← (HL) HL ← HL – 1 This instruction is used for block output of strings of data. The string of output data is loaded into the selected peripheral from memory at consecutive addresses, starting with the location addressed by the HL register and decreasing.
Page 150 Z380 ™ ANUAL ILOG OTDRW OUTPUT, DECREMENT AND REPEAT (WORD) OTDRW Operation: repeat until (BC=0) begin ← BC(15-0) BC(15-0) – 1 ← (DE) (HL) ← HL – 2 This instruction is used for block output of strings of data. The string of output data is loaded into the selected peripheral from memory at consecutive addresses, starting with the location addressed by the HL register and decreasing.
Page 151 ™ Z380 ANUAL ILOG OTIM OUTPUT INCREMENT MEMORY OTIM (C) ← (HL) Operation: ← C + 1 ← B – 1 HL ← HL + 1 This instruction is used for block output of strings of data to on-chip peripherals. No external I/O transaction will be generated as a result of this instruction, although the I/O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring.
Page 152 Z380 ™ ANUAL ILOG OTIMR OUTPUT, INCREMENT MEMORY REPEAT OTIMR Operation: repeat until (B=0) begin (C) ← (HL) ← C + 1 ← B – 1 HL ← HL + 1 This instruction is used for block output of strings of data to on-chip peripherals. No external I/O transaction will be generated as a result of this instruction, although the I/O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring.
Page 153 ™ Z380 ANUAL ILOG OTIR OUTPUT, INCREMENT AND REPEAT (BYTE) OTIR Operation: repeat until (B=0) begin ← B – 1 (C) ← (HL) HL ← HL + 1 This instruction is used for block output of strings of data. The string of output data is loaded into the selected peripheral from memory at consecutive addresses, starting with the location addressed by the HL register and increasing.
Page 154 Z380 ™ ANUAL ILOG OTIRW OUTPUT, INCREMENT AND REPEAT (WORD) OTIRW Operation: repeat until (BC=0) begin ← BC(15-0) BC(15-0) – 1 ← (DE) (HL) ← HL + 2 This instruction is used for block output of strings of data. The string of output data is loaded into the selected peripheral from memory at consecutive addresses, starting with the location addressed by the HL register and increasing.
Page 155 ™ Z380 ANUAL ILOG OUTPUT (BYTE) OUT (C),src src = R, IM (C) ← src Operation: The byte of data from the source is loaded into the selected peripheral. During the I/O transaction, the contents of the 32-bit BC register are placed on the address bus. Flags: Unaffected Unaffected...
Page 156 Z380 ™ ANUAL ILOG OUTW OUTPUT (WORD) OUTW (C),src src = R, IM (C) ← src(15-0) Operation: The word of data from the source is loaded into the selected peripheral. During the I/O transaction, the contents of the 32-bit BC register are placed on the address bus. Flags: Unaffected Unaffected...
Page 157 ™ Z380 ANUAL ILOG OUTPUT ACCUMULATOR OUT (n),A (n) ← A Operation: The byte of data from the accumulator is loaded into the selected peripheral. During the I/O transaction, the 8-bit peripheral address from the instruction is placed on the low byte of the address bus, the contents of the accumulator are placed on address lines A(15-8), and the high-order address lines are all zeros.
Page 158 Z380 ™ ANUAL ILOG OUT0 OUTPUT (TO PAGE 0) OUT0 (n),src src = R (n) ← src Operation: The byte of data from the source register is loaded into the selected on-chip peripheral. No external I/O transaction will be generated as a result of this instruction, although the I/O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring.
Page 159 ™ Z380 ANUAL ILOG OUTA OUTPUT DIRECT TO PORT ADDRESS (BYTE) OUT (nn),A (nn) ← A Operation: The byte of data from the accumulator is loaded into the selected peripheral. During the I/O transaction, the peripheral address from the instruction is placed on the address bus. Any bytes of address not specified in the instruction are driven on the address lines are all zeros.
Page 160 Z380 ™ ANUAL ILOG OUTAW OUTPUT DIRECT TO PORT ADDRESS (WORD) OUT (nn),HL Operation: (nn)← HL(15-0) The word of data from the HL register is loaded into the selected peripheral. During the I/O transaction, the peripheral address from the instruction is placed on the address bus. Any bytes of address not specified in the instruction are driven on the address lines are all zeros.
Page 161 ™ Z380 ANUAL ILOG OUTD OUTPUT AND DECREMENT (BYTE) OUTD ← B - 1 Operation: (C) ← (HL) HL ← HL - 1 This instruction is used for block output of strings of data. During the I/O transaction the 32-bit BC register is placed on the address bus. Note that the B register contains the loop count for this instruction so that A15-A8 are not useable as part of a fixed port address.
Page 162 Z380 ™ ANUAL ILOG OUTDW OUTPUT AND DECREMENT (WORD) OUTDW ← BC(15-0) - 1 Operation: BC(15-0) ← (HL) (DE) ← HL - 2 This instruction is used for block output of strings of data. During the I/O transaction the 32- bit DE register is placed on the address bus.
Page 163 ™ Z380 ANUAL ILOG OUTI OUTPUT AND INCREMENT (BYTE) OUTI ← B - 1 Operation: (C) ← (HL) HL ← HL + 1 This instruction is used for block output of strings of data. During the I/O transaction the 32- bit BC register is placed on the address bus.
Page 164 Z380 ™ ANUAL ILOG OUTIW OUTPUT AND INCREMENT (WORD) OUTIW ← BC(15-0) –1 Operation: BC(15-0) ← (HL) (DE) ← HL + 2 This instruction is used for block output of strings of data. During the I/O transaction the 32- bit DE register is placed on the address bus. First the BC register, used as a counter, is decremented by one.
Page 165 ™ Z380 ANUAL ILOG POP ACCUMULATOR POP dst dst = AF ← (SP) Operation: ← (SP+1) ← SP + 2 if (LW) then begin SP ← SP + 2 The contents of the memory location addressed by the Stack Pointer (SP) are loaded into the destination in ascending byte order from ascending address memory locations.
Page 166 Z380 ™ ANUAL ILOG POP CONTROL REGISTER POP dst dst = SR Operation: if (LW) then begin ← dst(6-0) (SP) ← dst(15-8) (SP+1) dst(23-16) ← (SP+2) dst(31-24) ← (SP+3) ← SP + 4 else begin ← dst(6-0) (SP) ← dst(15-8) (SP+1) dst(23-16) ←...
Page 167 ™ Z380 ANUAL ILOG POP REGISTER POP dst dst = R, RX Operation: if (LW) then begin ← dst(7-0 ) (SP) ← dst(15-8) (SP+1) dst(23-16) ← (SP+2) dst(31-24) ← (SP+3) ← SP + 4 else begin ← dst(7-0) (SP) ← dst(15-8) (SP+1) ←...
Page 168 Z380 ™ ANUAL ILOG PUSH PUSH ACCUMULATOR PUSH src src = AF Operation: if (LW) then begin ← SP - 4 ← F (SP) (SP+1) ← A (SP+2) ← 00h (SP+3) ← 00h else begin ← SP - 2 ← F (SP) (SP+1) ←...
Page 169 ™ Z380 ANUAL ILOG PUSH PUSH CONTROL REGISTER PUSH src src = SR Operation: if (LW) then begin ← SP - 4 ← src(7-0) (SP) (SP+1) ← src(15-8) (SP+2) ← src(23-16) (SP+3) ← src(31-24) else begin ← SP - 2 ←...
Page 170 Z380 ™ ANUAL ILOG PUSH PUSH IMMEDIATE PUSH src src = IM Operation: if (LW) then begin ← SP - 4 ← src(7-0) (SP) (SP+1) ← src(15-8) (SP+2) ← src(23-16) (SP+3) ← src(31-24) else begin ← SP - 2 ← src(7-0) (SP) (SP+1) ←...
Page 171 ™ Z380 ANUAL ILOG PUSH PUSH REGISTER PUSH src src = R, RX Operation: if (LW) then begin ← SP - 4 ← src(7-0) (SP) (SP+1) ← src(15-8) (SP+2) ← src(23-16) (SP+3) ← src(31-24) else begin ← SP - 2 ←...
Page 172 Z380 ™ ANUAL ILOG RESET BIT RES b, dst dst = R, IR, X dst(b) ← 0 Operation: The specified bit b within the destination operand is cleared to 0. The other bits in the destination are unaffected. The bit to be reset is specified by a 3-bit field in the instruction; this field contains the binary encoding for the bit number to be cleared.
Page 173 ™ Z380 ANUAL ILOG RESC RESET CONTROL BIT RESC mode mode = LCK, LW Operation: if (mode = LCK) then begin ← 0 SR(1) else begin ← 0 SR(6) When reseting Lock mode (LCK), the LCK bit (bit 1) in the Select Register (SR) is set to 0, enabling external bus requests.
Page 174 Z380 ™ ANUAL ILOG RETURN RET [cc] Operation: if (cc is TRUE) then begin if (XM) then begin ← PC(7-0) (SP) ← PC(15-8) (SP+1) ← PC(23-16) (SP+2) ← PC(31-24) (SP+3) ← SP + 4 else begin ← PC(7-0) (SP) ← PC(15-8) (SP+1) ←...
Page 175 ™ Z380 ANUAL ILOG RETB RETURN FROM BREAKPOINT ← SPC (31-0) Operation: PC (31-0) This instruction is used to return to a previously executing procedure at the end of a breakpoint. The contents of the Shadow Program Counter (SPC), which holds the address of the next instruction of the previously executing procedure, are loaded into the Program Counter (PC).
Page 176 Z380 ™ ANUAL ILOG RETI RETURN FROM INTERRUPT RETI Operation: if (XM) then begin ← PC(7-0) (SP) ← PC(15-8) (SP+1) PC(23-16) ← (SP+2) PC(31-24) ← (SP+3) ← SP + 4 else begin ← PC(7-0) (SP) ← PC(15-8) (SP+1) ← SP + 2 This instruction is used to return to a previously executing procedure at the end of a procedure entered by an interrupt.
Page 177 ™ Z380 ANUAL ILOG RETN RETURN FROM NONMASKABLE INTERRUPT RETN Operation: if (XM) then begin ← PC(7-0) (SP) ← PC(15-8) (SP+1) PC(23-16) ← (SP+2) PC(31-24) ← (SP+3) ← SP + 4 else begin ← PC(7-0) (SP) ← PC(15-8) (SP+1) ← SP + 2 ←...
Page 178 Z380 ™ ANUAL ILOG ROTATE LEFT (BYTE) RL dst dst = R, IR, X ← dst Operation: ← C dst(0) ← dst(7) ← tmp(n) for n = 0 to 6 dst(n+1) The contents of the destination operand are concatenated with the Carry flag and together they are rotated left one bit position.
Page 179 ™ Z380 ANUAL ILOG ROTATE LEFT (WORD) RLW dst dst = R, RX, IR, X ← dst Operation: ← C dst(0) ← dst(15) ← tmp(n) for n = 0 to 14 dst(n+1) The contents of the destination operand are concatenated with the Carry flag and together they are rotated left one bit position.
Page 180 Z380 ™ ANUAL ILOG ROTATE LEFT (ACCUMULATOR) ← A Operation: ← C A(0) ← A(7) A(n+1) ← tmp(n) for n = 0 to 6 The contents of the accumulator are concatenated with the Carry flag and together they are rotated left one bit position. Bit 7 of the accumulator is moved to the Carry flag and the Carry flag is moved to bit 0 of the accumulator.
Page 181 ™ Z380 ANUAL ILOG ROTATE LEFT CIRCULAR (BYTE) RLC dst dst = R, IR, X ← dst Operation: ← dst(7) ← tmp(7) dst(0) ← tmp(n) for n = 0 to 6 dst(n+1) The contents of the destination operand are rotated left one bit position. Bit 7 of the destination operand is moved to the bit 0 position and also replaces the Carry flag.
Page 182 Z380 ™ ANUAL ILOG RLCW ROTATE LEFT CIRCULAR (WORD) RLCW dst dst = R, RX, IR, X ← dst Operation: ← dst(15) ← tmp(15) dst(0) ← tmp(n) for n = 0 to 14 dst(n+1) The contents of the destination operand are rotated left one bit position. The most significant bit of the destination operand is moved to the bit 0 position and also replaces the Carry flag.
Page 183 ™ Z380 ANUAL ILOG RLCA ROTATE LEFT CIRCULAR (ACCUMULATOR) RLCA ← A Operation: ← A(7) ← tmp(7) A(0) A(n+1) ← tmp(n) for n = 0 to 6 The contents of the accumulator are rotated left one bit position. Bit 7 of the accumulator is moved to the bit 0 position and also replaces the Carry flag.
Page 184 Z380 ™ ANUAL ILOG ROTATE LEFT DIGIT ← A(3-0) Operation: tmp(3-0) ← dst(7-4) A(3-0) ← dst(3-0) dst(7-4) ← tmp(3-0) dst(3-0) The low digit of the accumulator is logically concatenated to the destination byte whose memory address is in the HL register. The resulting three-digit quantity is rotated to the left by one BCD digit (four bits).
Page 185 ™ Z380 ANUAL ILOG ROTATE RIGHT (BYTE) RR dst dst = R, IR, X ← dst Operation: dst(7) ← C ← dst(0) dst(n) ← tmp(n+1) for n = 0 to 6 The contents of the destination operand are concatenated with the Carry flag and together they are rotated right one bit position.
Page 186 Z380 ™ ANUAL ILOG ROTATE RIGHT (WORD) RRW dst dst = R, RX, IR, X ← dst Operation: ← dst(0) dst(15) ← C dst(n) ← tmp(n+1) for n = 0 to 14 The contents of the destination operand are concatenated with the Carry flag and together they are rotated right one bit position.
Page 187 ™ Z380 ANUAL ILOG ROTATE RIGHT (ACCUMULATOR) ← A Operation: ← C A(7) ← A(0) ← tmp(n+1) for n = 0 to 6 A(n) The contents of the accumulator are concatenated with the Carry flag and together they are rotated right one bit position. Bit 0 of the accumulator is moved to the Carry flag and the Carry flag is moved to bit 7 of the accumulator.
Page 188 Z380 ™ ANUAL ILOG ROTATE RIGHT CIRCULAR (BYTE) RRC dst dst = R, IR, X ← dst Operation: ← dst(0) dst(7) ← tmp(0) dst(n) ← tmp(n+1) for n = 0 to 6 The contents of the destination operand are rotated right one bit position. Bit 0 of the destination operand is moved to the bit 7 position and also replaces the Carry flag.
Page 189 ™ Z380 ANUAL ILOG RRCW ROTATE RIGHT CIRCULAR (WORD) RRCW dst dst = R, RX, IR, X ← dst Operation: ← dst(0) dst(15) ← tmp(0) dst(n) ← tmp(n+1) for n = 0 to 14 The contents of the destination operand are rotated right one bit position. Bit 0 of the destination operand is moved to the most significant bit position and also replaces the Carry flag.
Page 190 Z380 ™ ANUAL ILOG RRCA ROTATE RIGHT CIRCULAR (ACCUMULATOR) RRCA ← A Operation: ← A(0) ← tmp(0) A(7) ← tmp(n+1) for n = 0 to 6 A(n) The contents of the accumulator are rotated right one bit position. Bit 0 of the accumulator is moved to the bit 7 position and also replaces the Carry flag.
Page 191 ™ Z380 ANUAL ILOG ROTATE RIGHT DIGIT ← A(3-0) Operation: tmp(3-0) ← dst(3-0) A(3-0) ← dst(7-4) dst(3-0) ← tmp(3-0) dst(7-4) The low digit of the accumulator is logically concatenated to the destination byte whose memory address is in the HL register. The resulting three-digit quantity is rotated to the right by one BCD digit (four bits).
Page 192 Z380 ™ ANUAL ILOG RESTART RST address Operation: if (XM) then begin ← SP - 4 ← PC(7-0) (SP) (SP+1) ← PC(15-8) (SP+2) ← PC(23-16) (SP+3) ← PC(31-24) else begin ← SP - 2 ← PC(7-0) (SP) (SP+1) ← PC(15-8) ←...
Page 193 ™ Z380 ANUAL ILOG SUBTRACT WITH CARRY (BYTE) SBC A,src src = R, RX, IM, IR, X ← A - src - C Operation: The source operand together with the Carry flag is subtracted from the accumulator and the difference is stored in the accumulator. The contents of the source are unaffected. Two's complement subtraction is performed.
Page 194 Z380 ™ ANUAL ILOG SUBTRACT WITH CARRY (WORD) SBC HL,src dst = HL src = BC, DE, HL, SP ← HL(15-0) - src(15-0) - C Operation: HL(15-0) The source operand together with the Carry flag is subtracted from the HL register and the difference is stored in the HL register.
Page 195 ™ Z380 ANUAL ILOG SBCW SUBTRACT WITH CARRY (WORD) SBCW [HL,]src src = R, RX, IM, X HL(15-0) ← HL(15-0) - src(15-0) - C Operation: The source operand together with the Carry flag is subtracted from the HL register and the difference is stored in the HL register.
Page 196 Z380 ™ ANUAL ILOG SET CARRY FLAG ← 1 Operation: The Carry flag is set to 1. Flags: Unaffected Unaffected Cleared Unaffected Cleared Addressing Execute Mode Syntax Instruction Format Time Note 00110111 5-162 DC-8297-03...
Page 197 ™ Z380 ANUAL ILOG SET BIT SET b, dst dst = R, IR, X dst(b) ← 1 Operation: The specified bit b within the destination operand is set to 1. The other bits in the destination are unaffected. The bit to be set is specified by a 3-bit field in the instruction; this field contains the binary encoding for the bit number to be set.
Page 198 Z380 ™ ANUAL ILOG SETC SET CONTROL BIT SETC mode mode = LCK, LW, XM Operation: if (mode = LCK) then begin ← 1 SR(1) else if (mode = LW) then begin ← 1 SR(6) else begin ← 1 SR(7) When setting Lock mode (LCK), the LCK bit (bit 1) in the Select Register (SR) is set to 1, disabling external bus requests.
Page 199 ™ Z380 ANUAL ILOG SHIFT LEFT ARITHMETIC (BYTE) SLA dst dst = R, IR, X ← dst Operation: ← dst(7) ← 0 dst(0) ← tmp(n) for n = 0 to 6 dst(n+1) The contents of the destination operand are shifted left one bit position. Bit 7 of the destination operand is moved to the Carry flag and zero is shifted into bit 0 of the destination.
Page 200 Z380 ™ ANUAL ILOG SLAW SHIFT LEFT ARITHMETIC (WORD) SLAW dst dst = R, RX, IR, X ← dst Operation: ← 0 dst(0) ← dst(15) ← tmp(n) for n = 0 to 14 dst(n+1) The contents of the destination operand are shifted left one bit position. The most significant bit of the destination operand is moved to the Carry flag and zero is shifted into bit 0 of the destination.
Page 201 ™ Z380 ANUAL ILOG SLEEP Operation: if (STBY not enabled) then CPU Halts else Z380 enters Standby mode With Standby mode disabled, this instruction is interpreted and executed as a HALT instruction. With Standby mode enabled, executing this instruction causes all device operation to stop, thus minimizing power dissipation.
Page 202 Z380 ™ ANUAL ILOG SHIFT RIGHT ARITHMETIC (BYTE) SRA dst dst = R, IR, X ← dst Operation: ← dst(0) dst(7) ← tmp(7) dst(n) ← tmp(n+1) for n = 0 to 6 The contents of the destination operand are shifted right one bit position. Bit 0 of the destination operand is moved to the Carry flag and bit 7 remains unchanged.
Page 203 ™ Z380 ANUAL ILOG SRAW SHIFT RIGHT ARITHMETIC (WORD) SRAW dst dst = R, RX, IR, X ← dst Operation: ← dst(0) dst(15) ← tmp(15) dst(n) ← tmp(n+1) for n = 0 to 14 The contents of the destination operand are shifted right one bit position. Bit 0 of the destination operand is moved to the Carry flag and the most significant bit remains unchanged.
Page 204 Z380 ™ ANUAL ILOG SHIFT RIGHT LOGICAL (BYTE) SRL dst dst = R, IR, X ← dst Operation: ← dst(0) dst(7) ← 0 dst(n) ← tmp(n+1) for n = 0 to 6 The contents of the destination operand are shifted right one bit position. Bit 0 of the destination operand is moved to the Carry flag and zero is shifted into bit 7 of the destination.
Page 205 ™ Z380 ANUAL ILOG SRLW SHIFT RIGHT LOGICAL (WORD) SRLW dst dst = R, RX, IR, X ← dst Operation: ← dst(0) dst(15) ← 0 dst(n) ← tmp(n+1) for n = 0 to 14 The contents of the destination operand are shifted right one bit position. Bit 0 of the destination operand is moved to the Carry flag and zero is shifted into the most significant bit of the destination.
Page 206 Z380 ™ ANUAL ILOG SUBTRACT (BYTE) SUB A,src src = R, RX, IM, IR, X ← A - src Operation: The source operand is subtracted from the accumulator and the difference is stored in the accumulator. The contents of the source are unaffected. Two's complement subtraction is performed.
Page 207 ™ Z380 ANUAL ILOG SUBTRACT (WORD) SUB HL,src src = DA Operation: if (XM) then begin ← HL(31-0) HL(31-0) - src(31-0) else begin ← HL(15-0) HL(15-0) - src(15-0) The source operand is subtracted from the HL register and the difference is stored in the HL register.
Page 208 Z380 ™ ANUAL ILOG SUBTRACT FROM STACK POINTER (WORD) SUB SP,src src = IM Operation: if (XM) then begin ← SP(31-0) SP(31-0) – src(31-0) else begin ← SP(15-0) SP(15-0) – src(15-0) The source operand is subtracted from the SP register and the difference is stored in the SP register.
Page 209 ™ Z380 ANUAL ILOG SUBW SUBTRACT (WORD) SUBW [HL,]src src = R, RX, IM, X ← HL(15-0) - src(15-0) Operation: HL(15-0) The source operand is subtracted from the HL register and the difference is stored in the HL register. The contents of the source are unaffected. Two's complement subtraction is performed.
Page 210 Z380 ™ ANUAL ILOG SWAP SWAP UPPER REGISTER WORD WITH LOWER REGISTER WORD SWAP src src = R, RX src(31-16) ↔ src(15-0) Operation: The contents of the most significant word of the source are exchanged with the contents of the least significant word of the source. Flags: Unaffected Unaffected...
Page 211 ™ Z380 ANUAL ILOG TEST (BYTE) TST src src = R, IM, IR Operation: A AND src A logical AND operation is performed between the corresponding bits of the source operand and the accumulator. The contents of both the accumulator and the source are unaffected; only the flags are modified as a result of this instruction.
Page 212 Z380 ™ ANUAL ILOG TSTIO TEST I/O PORT TSTIO src src = IM Operation: (C) AND src A logical AND operation is performed between the corresponding bits of the source and the contents of the I/O location. The contents of both the I/O location and the source are unaffected;...
Page 213 ™ Z380 ANUAL ILOG EXCLUSIVE OR (BYTE) XOR [A,]src src = R, RX, IM, IR, X ← A XOR src Operation: A logical EXCLUSIVE OR operation is performed between the corresponding bits of the source operand and the accumulator and the result is stored in the accumulator. A 1 bit is stored wherever the corresponding bits in the two operands are different;...
Page 214 Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL y: 0 for IX, 1 for IY © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo-...
Page 215 Z380 ™ ANUAL ILOG ’s M ANUAL HAPTER NTERRUPTS RAPS 6.1 INTRODUCTION Exceptions are conditions that can alter the normal flow of A hardware reset overrides all other conditions, including ™ program execution. The Z380 CPU supports three kinds Interrupts and Traps. It occurs when the /RESET line is of exceptions;...
Page 216 Z380 ™ ANUAL ILOG 6.2 INTERRUPTS (Continued) In an Interrupt acknowledge transaction, address outputs MPU provides an Interrupt Register Extension, whose A31-A4 are driven to logic 1. One output among A3-A0 is contents are always output as the address bus signals driven to logic 0 to indicate the maskable interrupt request A31-A16 when fetching the starting addresses of service being acknowledged.
Page 217 Z380 ™ ANUAL ILOG end of the /NMI interrupt service routine, execution of the 6.2.2.1 IEF1, IEF2 IEF1 controls the overall enabling and disabling of all on- Return From Nonmaskable Interrupt instruction, RETN, chip peripheral and external maskable Interrupt requests. automatically copies the state of IEF2 back to IEF1.
Page 218 Z380 ™ ANUAL ILOG 6.2.2.5 Trap and Break Register TRPBK: 00000019H D7-D2 Reserved. Some of these bits are reserved for development support functions. Read as 0, should write to as 0. D1 TF (Trap on Instruction Fetch). TF goes active to logic Reset Value 1 when an undefined opcode fetched in the instruction Trap on...
Page 219 Z380 ™ ANUAL ILOG 6.4 NONMASKABLE INTERRUPT The Nonmaskable Interrupt Input /NMI is edge sensitive, 2. The state of IEF1 is copied to IEF2, then IEF1 is with the Z380 MPU internally latching the occurrence of its cleared. falling edge. When the latched version of /NMI is recog- nized, the following operations are performed.
Page 220 Z380 ™ ANUAL ILOG 6.5.4 Interrupt Mode 3 Response for Maskable Interrupt /INT0 (Continued) Native (one word) or Extended mode (two words) in effect. address of the service routine is word-sized if the Z380 IEF1 and IEF2 are reset to logic 0 so as to disable further MPU is in Native mode and Long Word-sized if in the maskable Interrupt requests.
Page 221 ™ ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 222 ANUAL ILOG ’s M ANUAL HAPTER ESET 7.1 INTRODUCTION The Z380 CPU is placed in a dormant state when the with reference to the falling edge of BUSCLK. On the Z380 /RESET input is asserted. All its operations are terminated, MPU implementation, with the proper setup and hold times including any interrupt, bus request, or bus transaction being met, IOCLK’s first rising edge is 11.5 BUSCLK...
Page 223 ANUAL ILOG Table 7-1. Effect of a Reset on Z380 CPU and Related I/O Registers Register Reset Value Comments Program Counter 00000000 PCz, PC Stack Pointer 00000000 SPz, SP 000000 Iz, I Select Register 00000000 Register Bank 0 Selected: AF, Main Bank, IX, IY Native Mode Maskable Interrupts Disabled, in Mode 0 Bus Request Lock-Off...
Page 224 ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 225 ANUAL ILOG ’s M ANUAL PPENDIX ™ Z380 CPU I NSTRUCTION ORMATS For the opcode escape byte, the Z380 CPU uses 0DDH Four formats are used to generate the machine language and 0FDH as well, which on the Z80 CPU, these are used bit encoding for the Z380 CPU instructions.
Page 226 ANUAL ILOG The four instruction formats are shown in Tables A-1 the symbol “A.esc” is used to indicate the presence of an through A-4. Within each format, several different configu- addressing mode escape byte, “O.esc” is used to indicate rations are possible, depending on whether the instruction the presence of an opcode escape byte, “disp.”...
Page 227 ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 228 ANUAL ILOG ’s M ANUAL PPENDIX Z380 ™ NSTRUCTIONS IN LPHABETIC RDER This Appendix contains a quick reference guide for pro- with DDIR IM to expand its immediate constant, “X” means gramming. It has the Z380 instructions sorted alphabeti- that the operation of the instruction is affected by the XM cally.
Page 229 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code A,(HL) HL,SP A,(IX+12H) 8E 12 IX,BC A,(IY+12H) 8E 12 IX,DE IX,IX IX,SP IY,BC IY,DE IY,IY IY,SP A,IXL SP,1234H 82 34 12 A,IXU ADDW (IX+12H) C6 12 A,IYL ADDW (IY+12H) C6 12 A,IYU...
Page 230 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code ANDW (IX+12H) E6 12 ANDW (IY+12H) E6 12 ANDW 1234H A6 34 12 4,(HL) ANDW 4,(IX+12H) CB 12 66 ANDW 4,(IY+12H) CB 12 66 ANDW ANDW HL,(IX+12H) E6 12 ANDW HL,(IY+12H) E6 12...
Page 231 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code CALL NV, 1234H E4 34 CALL Z,1234H CC 34 HL,IX DD BF CALR 123456H FD CD 56 34 12 DD BF CALR 1234H DD CD 34 12 DD BD CALR ED CD 12 DD BC...
Page 232 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code FD 2B BC,BC’ ED CB 30 FD 2D BC,DE ED 05 FD 25 BC,HL ED 0D BC,IX ED 03 BC,IY ED 0B DECW C,C’ CB 31 DECW D,D’ CB 32 DECW DE,DE’...
Page 233 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code C,12H 38 12 NC,123456H FD 30 56 34 12 NC,1234H DD 30 34 12 NC,12H 30 12 NZ,123456H FD 20 56 34 12 NZ,1234H DD 20 34 12 NZ,12H 20 12 NZ,12H...
Page 234 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code (IX+12H),IY DD CB 12 2B BC,(1234H) ED 4B 34 12 (IX+12H),L DD 75 BC,(BC) DD 0C (IY+12H),34H I FD 36 34 12 BC,(DE) DD 0D (IY+12H),A FD 77 BC,(HL) DD 0F (IY+12H),B...
Page 235 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code DE,IX DD 1B IX,HL DD 37 DE,IY FD 1B IX,IY DD 27 E,(HL) IXL,12H DD 2E E,(IX+12H) DD 5E IXL,A DD 6F E,(IY+12H) FD 5E IXL,B DD 68 E,12H 1E 12 IXL,C...
Page 236 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code MULTW (IX+12H) DD CB 12 92 MULTW (IY+12H) FD CB 12 92 ED 4F MULTW 1234H ED CB 97 34 12 SP,(1234H) I ED 7B 34 12 MULTW ED CB 90 SP,1234H 31 34...
Page 237 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code PUSH AF ED B5 PUSH BC ED B7 HL,(IX+12H) I DD F6 12 PUSH DE HL,(IY+12H) I FD F6 12 PUSH HL PUSH IX DD E5 HL,1234H ED B6 34 12 PUSH IY FD E5 HL,BC...
Page 238 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code CB 17 CB A3 CB 10 CB A4 CB 11 CB A5 CB 12 5,(HL) CB AE CB 13 5,(IX+12H) I DD CB 12 AE CB 14 5,(IY+12H) I FD CB 12 AE CB 15 CB AF...
Page 239 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code CB 0C SBCW HL,(IY+12H) FD DE 12 CB 0D SBCW HL,1234H ED 9E 34 12 RRCA SBCW HL,BC ED 9C RRCW (HL) ED CB 0A SBCW HL,DE ED 9D RRCW (IX+12H) DD CB 12 0A SBCW HL,HL...
Page 240 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code CB E0 SLAW HL ED CB 23 CB E1 SLAW IX ED CB 24 CB E2 SLAW IY ED CB 25 CB E3 ED 76 CB E4 (HL) CB 2E CB E5 (IX+12H)
Page 241 ANUAL ILOG Source Code Mode Object Code Source Code Mode Object Code A,IYU FD 94 A,IYL FD AD A,IYU FD AC HL,(1234H) ED D6 34 12 SP,1234H ED 92 34 12 SUBW (IX+12H) DD D6 12 SUBW (IY+12H) FD D6 12 SUBW 1234H ED 96 34 12...
Page 242 ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 243 ANUAL ILOG ’s M ANUAL PPENDIX ™ Z380 NSTRUCTION IN UMERIC RDER The following Appendix has the Z380 instructions sorted that the operation of the instruction is affected by the XM by numeric order. status bit, and “L” means that the instruction is affected by LW status bit, or can be used with DDIR LW or DDIR W.
Page 244 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode 01 34 12 BC,1234H 30 12 NC,12H (BC),A 31 34 12 SP,1234H 32 34 12 (1234H),A INCW INCW (HL) 06 12 B,12H (HL) RLCA 36 12 (HL),12H AF,AF' HL,BC 38 12 C,12H...
Page 245 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode H,(HL) A,(HL) L,(HL) (HL),B (HL),C (HL),D (HL),E (HL),H (HL),L HALT (HL) (HL),A A,(HL) A,(HL) A,(HL) (HL) A,(HL) A,(HL) A,(HL) (HL) A,(HL)
Page 246 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode CB 1A CB 1B CB 1C CB 1D CB 1E (HL) CB 1F CB 20 CB 21 CB 22 CB 23 CB 24 CB 25 CB 26 (HL) (HL) CB 27 A,(HL)
Page 247 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode CB 51 CB 87 CB 52 CB 88 CB 53 CB 89 CB 54 CB 8A CB 55 CB 8B CB 56 2,(HL) CB 8C CB 57 CB 8D CB 58 CB 8E 1,(HL)
Page 248 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode CB BD CB F3 CB BE 7,(HL) CB F4 CB BF CB F5 CB C0 CB F6 6,(HL) CB C1 CB F7 CB C2 CB F8 CB C3 CB F9 CB C4 CB FA...
Page 249 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode DD 23 DD 63 IXU,E DD 23 INCW IX DD 64 IXU,IXU DD 24 DD 65 IXU,IXL DD 25 DD 66 12 H,(IX+12H) DD 26 12 IXU,12H DD 67 IXU,A DD 27 IX,IY...
Page 250 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode DD AC DD CB 12 2B (IX+12H),IY DD AD A,IXL DD CB 12 2E (IX+12H) DD AD DD CB 12 31 HL,(SP+12H) I DD AE 12 (IX+12H) DD CB 12 33 HL,(IX+12H) DD AE 12 A,(IX+12H)
Page 251 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode DD E3 (SP),IX ED 0F DD E4 34 12 CALR PO,1234H ED 10 12 D,(12H) DD E5 PUSH ED 11 12 OUT0 (12H),D DD E6 12 ANDW (IX+12H) ED 12 DE,BC DD E6 12...
Page 252 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode ED 52 HL,DE ED 8D ADCW HL,DE ED 53 34 12 (1234H),DE ED 8E 34 12 ADCW 1234H ED 54 NEGW HL ED 8E 34 12 ADCW HL,1234H ED 54 NEGW ED 8F...
Page 253 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode ED B5 ED CB 28 SRAW BC ED B5 HL,DE ED CB 29 SRAW DE ED B6 34 12 1234H ED CB 2A SRAW (HL) ED B6 34 12 HL,1234H ED CB 2B SRAW HL...
Page 254 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode ED CB BC DIVUW HL,IX FA 34 12 S,1234H ED CB BC DIVUW ED CB BD DIVUW HL,IY FC 34 12 CALL S, M,1234H ED CB BD DIVUW FD 01 (BC),IY ED CB BF...
Page 255 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode FD 3F (HL),HL FD 97 SUBW IY FD 44 B,IYU FD 9C A,IYU FD 45 B,IYL FD 9D A,IYL FD 46 12 B,(IY+12H) FD 9E 12 A,(IY+12H) FD 4C C,IYU FD 9F SBCW HL,IY...
Page 256 ANUAL ILOG Object Code Source Code Mode Object Code Source Code Mode FD CB 12 1A (IY+12H) FD D8 LDCTL YSR,A FD CB 12 1B (IY+12H),DE FD D9 EXXY FD CB 12 1E (IY+12H) FD DA 01 LDCTL YSR,01H FD CB 12 21 IY,(SP+12H) FD DB 34 12 INAW...
Page 257 ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 258 ANUAL ILOG ’s M ANUAL PPENDIX NSTRUCTIONS FFECTED BY ORMAL XTENDED This Appendix has two sets of tables. Each table is a Extended mode of operation, and the Table D-2 has the subset of the Table in the Appendix B. The Table D-1 has instructions which works differently in Word/Long Word the instructions which works differently in the Native and mode of operation.
Page 259 ANUAL ILOG Table D-1. Instructions operating differently in Native or Extended mode of operation. Source Code Object Code Source Code Object Code DECW DE HL,BC DECW HL HL,DE DECW IX HL,HL DECW IY HL,SP DECW SP IX,BC DJNZ 123456H IX,DE DJNZ 1234H IX,IX DJNZ 12H...
Page 260 ANUAL ILOG Source Code Object Code RETN Table D-2. Instructions operates different in Long Word Modes. Source Code Object Code Source Code Object Code BC,DE (SP),HL BC,HL (SP),IX BC,IX (SP),IY BC,IY BC,BC’ DE,(BC) BC,DE DE,(DE) BC,HL DE,(HL) BC,IX DE,BC BC,IY DE,DE DE,DE’...
Page 261 PUSH IX PUSH IY PUSH SR © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.
Page 262 ANUAL ILOG ’s M ANUAL PPENDIX NSTRUCTIONS FFECTED BY DDIR IM I NSTRUCTIONS This Appendix has instructions which can be used with the Table E-2. Valid with DDIR IB. XM bit status does not Decoder Directive(s) Extend Immediate. There are eight affect the operation.
Page 263 ANUAL ILOG Table E-3. Valid with DDIR IB in Long Word mode. (IX+1234H) XM bit status does not affect the operation. (Either (IY+1234H) with DDIR IB,LW or DDIR IB with LW bit set.) HL,(IX+1234H) HL,(IY+1234H) BC,123456H (IX+1234H) DE,123456H (IY+1234H) HL,123456H DIVUW (IX+1234H) IX,123456H...
Page 264 ANUAL ILOG 5,(IX+1234H) 12 EE (IY+1234H) 5,(IY+1234H) 12 EE A,(IX+1234H) 6,(IX+1234H) 12 F6 A,(IY+1234H) 6,(IY+1234H) 12 F6 (IX+1234H) 7,(IX+1234H) 12 FE (IY+1234H) 7,(IY+1234H) 12 FE HL,(IX+1234H) (IX+1234H) 12 26 HL,(IY+1234H) (IY+1234H) 12 26 OUTA (123456H),A SLAW (IX+1234H) 12 22 OUTAW (123456H),HL SLAW (IY+1234H) 12 22...
Page 265 ANUAL ILOG Table E-5. Valid with DDIR IW in Exteded mode. LW Table E-6. Valid with DDIR IW. XM bit status does bit status does not affect the operation not affect the operation. Transfer size determined by LW bit HL,(12345678H) C6 78 56 34 12 SP,12345678H 82 78 56 34 12...
Page 266 ANUAL ILOG Table E-7. Valid with DDIR IW in Long Word mode. HL,(IX+123456H) DD FE 56 34 12 XM bit status does not affect the operation. (Either HL,(IY+123456H) FD FE 56 34 12 with DDIR IW,LW or DDIR IW with LW bit set.) (IX+123456H) DD 35 56 34 12 (IY+123456H)
Page 267 ANUAL ILOG A,(IX+123456H) DD B6 56 34 12 4,(IY+123456H) FD CB 56 34 12 E6 A,(IY+123456H) FD B6 56 34 12 5,(IX+123456H) DD CB 56 34 12 EE (IX+123456H) DD F6 56 34 12 5,(IY+123456H) FD CB 56 34 12 EE (IY+123456H) FD F6 56 34 12 6,(IX+123456H)
Page 268 ANUAL ILOG © 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No Zilog’s products are not authorized for use as critical compo- part of this document may be copied or reproduced in any form nents in life support devices or systems unless a specific written or by any means without the prior written consent of Zilog, Inc.

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Page 83: Enable Interrupts

Page 144: Nop No Operation