ZiLOG Z80380 User Manual page 127

Z
ILOG
LDCTL dst,src
Operation: if (dst = SR) then begin
SR(31-24) ←
SR(23-16) ←
SR(15-8)
end
else begin
dst
end
The contents of the source are loaded into the destination.
S: Unaffected
Flags:
Z: Unaffected
H: Unaffected
V: Unaffected
N: Unaffected
C: Unaffected
Load into Control Register
Addressing
Mode Syntax
R: LDCTL SR,A
LDCTL Rd,A
IM: LDCTL SR,n
LDCTL Rd,n
Field Encodings: qq: 01 for XSR, 10 for DSR, 11 for YSR
Load from Control Register
Addressing
Mode Syntax
R: LDCTL A,Rs
Field Encodings: qq: 01 for XSR, 10 for DSR, 11 for YSR
DC-8297-03
dst = DSR, XSR, YSR
src = A, IM
or
dst = A
src = DSR, XSR, YSR
or
dst = SR
src = A, IM
src
src
←
src
←
src
Instruction Format
11011101 11001000
11qq1101 11011000
11011101 11001010 ——n—
11qq1101 11011010 ——n—
Instruction Format
11qq1101 11010000
LOAD CONTROL REGISTER (BYTE)
Execute
Time
4
4
4
4
Execute
Time
2
™
Z380
U ' M
SER S ANUAL
LDCTL
Note
Note
5-93