ZiLOG Z80380 User Manual page 60

Z
ILOG
ADDW
ADD (WORD)
ADDW [HL,]src
Operation: HL(15-0)
The source operand is added to the HL register and the sum is stored in the HL register. The
contents of the source are unaffected. Two's complement addition is performed.
Flags: S: Set if the result is negative; cleared otherwise
Z: Set if the result is zero; cleared otherwise
H: Set if there is a carry from bit 11 of the result; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise
N: Cleared
C: Set if there is a carry from the most significant bit of the result; cleared otherwise
Addressing
Mode Syntax
R: ADDW [HL,]R
RX: ADDW [HL,]RX
ADDW [HL,]nn
IM:
X: ADDW [HL,](XY+d)
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y: 0 for IX, 1 for IY
5-26
src = R, RX, IM, X
← HL(15-0) + src(15-0)
Instruction Format
11101101 100001rr
11y11101 10000111
11101101 10000110 -n(low)- n(high)-
11y11101 11000110 —d—
Z380 ™
U ' M
SER S ANUAL
Execute
Time Note
2
2
2
4+r I
DC-8297-03