Silicon Laboratories C8051F120 Manual page 9

LIST OF FIGURES
1. SYSTEM OVERVIEW .........................................................................................................19
Figure 1.1. C8051F120/124 Block Diagram..........................................................................21
Figure 1.2. C8051F121/125 Block Diagram..........................................................................22
Figure 1.3. C8051F122/126 Block Diagram..........................................................................23
Figure 1.4. C8051F123/127 Block Diagram..........................................................................24
Figure 1.5. On-Board Clock and Reset..................................................................................26
Figure 1.6. On-Chip Memory Map ........................................................................................27
Figure 1.7. Development/In-System Debug Diagram ...........................................................28
Figure 1.8. MAC0 Block Diagram ........................................................................................29
Figure 1.9. Digital Crossbar Diagram....................................................................................30
Figure 1.10. PCA Block Diagram............................................................................................31
Figure 1.11. 12-Bit ADC Block Diagram................................................................................33
Figure 1.12. 8-Bit ADC Diagram ............................................................................................34
Figure 1.13. Comparator and DAC Diagram...........................................................................35
2. ABSOLUTE MAXIMUM RATINGS ..................................................................................36
3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................37
4. PINOUT AND PACKAGE DEFINITIONS........................................................................39
Figure 4.1. TQFP-100 Pinout Diagram..................................................................................44
Figure 4.2. TQFP-100 Package Drawing...............................................................................45
Figure 4.3. TQFP-64 Pinout Diagram....................................................................................46
Figure 4.4. TQFP-64 Package Drawing.................................................................................47
5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) ..................................................................49
Figure 5.1. 12-Bit ADC0 Functional Block Diagram............................................................49
Figure 5.2. Typical Temperature Sensor Transfer Function..................................................50
Figure 5.3. ADC0 Track and Conversion Example Timing ..................................................52
Figure 5.4. ADC0 Equivalent Input Circuits .........................................................................53
Figure 5.5. AMX0CF: AMUX0 Configuration Register.......................................................54
Figure 5.6. AMX0SL: AMUX0 Channel Select Register .....................................................55
Figure 5.7. ADC0CF: ADC0 Configuration Register ...........................................................56
Figure 5.8. ADC0CN: ADC0 Control Register .....................................................................57
Figure 5.9. ADC0H: ADC0 Data Word MSB Register.........................................................58
Figure 5.10. ADC0L: ADC0 Data Word LSB Register ..........................................................58
Figure 5.11. ADC0 Data Word Example.................................................................................59
Figure 5.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register...............................60
Figure 5.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register ................................60
Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register ....................................61
Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register .....................................61
Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data .62
Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....63
Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data....64
Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data.......65
6. ADC0 (10-BIT ADC, C8051F122/3/6/7 ONLY) ..................................................................67
C8051F120/1/2/3/4/5/6/7
Rev. 1.2 9