Silicon Laboratories C8051F120 Manual page 11

Figure 10.1. Voltage Reference Functional Block Diagram .................................................109
Figure 10.2. REF0CN: Reference Control Register ..............................................................110
11. COMPARATORS................................................................................................................111
Figure 11.1. Comparator Functional Block Diagram ............................................................111
Figure 11.2. Comparator Hysteresis Plot...............................................................................113
Figure 11.3. CPT0CN: Comparator0 Control Register .........................................................114
Figure 11.4. CPT0MD: Comparator0 Mode Selection Register ...........................................115
Figure 11.5. CPT1CN: Comparator1 Control Register .........................................................116
Figure 11.6. CPT1MD: Comparator1 Mode Selection Register ...........................................117
12. CIP-51 MICROCONTROLLER........................................................................................119
Figure 12.1. CIP-51 Block Diagram .....................................................................................119
Figure 12.2. Memory Map .....................................................................................................125
Figure 12.3. PSBANK: Program Space Bank Select Register ..............................................126
Figure 12.4. Address Memory Map for Instruction Fetches..................................................126
Figure 12.5. SFR Page Stack .................................................................................................129
Figure 12.6. SFR Page Stack While Using SFR Page 0x0F To Access Port 5 .....................130
Figure 12.7. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs ..............131
Figure 12.8. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR...........132
Figure 12.9. SFR Page Stack Upon Return From PCA Interrupt ..........................................133
Figure 12.10. SFR Page Stack Upon Return From ADC2 Window Interrupt.......................134
Figure 12.11. SFRPGCN: SFR Page Control Register..........................................................135
Figure 12.12. SFRPAGE: SFR Page Register .......................................................................135
Figure 12.13. SFRNEXT: SFR Next Register .......................................................................136
Figure 12.14. SFRLAST: SFR Last Register ........................................................................136
Figure 12.15. SP: Stack Pointer .............................................................................................143
Figure 12.16. DPL: Data Pointer Low Byte ..........................................................................143
Figure 12.17. DPH: Data Pointer High Byte .........................................................................143
Figure 12.18. PSW: Program Status Word ............................................................................144
Figure 12.19. ACC: Accumulator..........................................................................................145
Figure 12.20. B: B Register ...................................................................................................145
Figure 12.21. IE: Interrupt Enable .........................................................................................149
Figure 12.22. IP: Interrupt Priority ........................................................................................150
Figure 12.23. EIE1: Extended Interrupt Enable 1 .................................................................151
Figure 12.24. EIE2: Extended Interrupt Enable 2 .................................................................152
Figure 12.25. EIP1: Extended Interrupt Priority 1.................................................................153
Figure 12.26. EIP2: Extended Interrupt Priority 2.................................................................154
Figure 12.27. PCON: Power Control.....................................................................................156
13. MULTIPLY AND ACCUMULATE (MAC0) ...................................................................157
Figure 13.1. MAC0 Block Diagram ......................................................................................157
Figure 13.2. Integer Mode Data Representation....................................................................158
Figure 13.3. Fractional Mode Data Representation ...............................................................158
Figure 13.4. MAC0 Pipeline..................................................................................................159
Figure 13.5. Multiply and Accumulate Example...................................................................160
Figure 13.6. Multiply Only Example.....................................................................................161
Figure 13.7. MAC0 Accumulator Shift Example ..................................................................161
C8051F120/1/2/3/4/5/6/7
Rev. 1.2 11