Silicon Laboratories C8051F120 Manual page 13

Figure 18.1. EMI0CN: External Memory Interface Control .................................................201
Figure 18.2. EMI0CF: External Memory Configuration .......................................................201
Figure 18.3. Multiplexed Configuration Example.................................................................202
Figure 18.4. Non-multiplexed Configuration Example .........................................................203
Figure 18.5. EMIF Operating Modes.....................................................................................204
Figure 18.6. EMI0TC: External Memory Timing Control ....................................................206
Figure 18.7. Non-multiplexed 16-bit MOVX Timing ...........................................................207
Figure 18.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................208
Figure 18.9. Non-multiplexed 8-bit MOVX with Bank Select Timing.................................209
Figure 18.10. Multiplexed 16-bit MOVX Timing .................................................................210
Figure 18.11. Multiplexed 8-bit MOVX without Bank Select Timing .................................211
Figure 18.12. Multiplexed 8-bit MOVX with Bank Select Timing.......................................212
19. PORT INPUT/OUTPUT .....................................................................................................215
Figure 19.1. Port I/O Cell Block Diagram.............................................................................215
Figure 19.2. Port I/O Functional Block Diagram ..................................................................216
Figure 19.3. Priority Crossbar Decode Table ........................................................................217
Figure 19.4. Priority Crossbar Decode Table ........................................................................220
Figure 19.5. Priority Crossbar Decode Table ........................................................................221
Figure 19.6. Crossbar Example: ............................................................................................223
Figure 19.7. XBR0: Port I/O Crossbar Register 0 .................................................................224
Figure 19.8. XBR1: Port I/O Crossbar Register 1 .................................................................225
Figure 19.9. XBR2: Port I/O Crossbar Register 2 .................................................................226
Figure 19.10. P0: Port0 Data Register ...................................................................................227
Figure 19.11. P0MDOUT: Port0 Output Mode Register.......................................................227
Figure 19.12. P1: Port1 Data Register ...................................................................................228
Figure 19.13. P1MDIN: Port1 Input Mode Register .............................................................228
Figure 19.14. P1MDOUT: Port1 Output Mode Register.......................................................229
Figure 19.15. P2: Port2 Data Register ...................................................................................229
Figure 19.16. P2MDOUT: Port2 Output Mode Register.......................................................230
Figure 19.17. P3: Port3 Data Register ...................................................................................230
Figure 19.18. P3MDOUT: Port3 Output Mode Register.......................................................231
Figure 19.19. P4: Port4 Data Register ...................................................................................233
Figure 19.20. P4MDOUT: Port4 Output Mode Register.......................................................233
Figure 19.21. P5: Port5 Data Register ...................................................................................234
Figure 19.22. P5MDOUT: Port5 Output Mode Register.......................................................234
Figure 19.23. P6: Port6 Data Register ...................................................................................235
Figure 19.24. P6MDOUT: Port6 Output Mode Register.......................................................235
Figure 19.25. P7: Port7 Data Register ...................................................................................236
Figure 19.26. P7MDOUT: Port7 Output Mode Register.......................................................236
20. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................237
Figure 20.1. SMBus0 Block Diagram ...................................................................................237
Figure 20.2. Typical SMBus Configuration ..........................................................................238
Figure 20.3. SMBus Transaction ...........................................................................................239
Figure 20.4. Typical Master Transmitter Sequence...............................................................240
Figure 20.5. Typical Master Receiver Sequence ...................................................................240
C8051F120/1/2/3/4/5/6/7
Rev. 1.2 13