Silicon Laboratories C8051F120 Manual page 12

C8051F120/1/2/3/4/5/6/7
Figure 13.8. MAC0CF: MAC0 Configuration Register ........................................................162
Figure 13.9. MAC0STA: MAC0 Status Register ..................................................................163
Figure 13.10. MAC0AH: MAC0 A High Byte Register .......................................................163
Figure 13.11. MAC0AL: MAC0 A Low Byte Register ........................................................164
Figure 13.12. MAC0BH: MAC0 B High Byte Register........................................................164
Figure 13.13. MAC0BL: MAC0 B Low Byte Register.........................................................164
Figure 13.14. MAC0ACC3: MAC0 Accumulator Byte 3 Register.......................................164
Figure 13.15. MAC0ACC2: MAC0 Accumulator Byte 2 Register.......................................165
Figure 13.16. MAC0ACC1: MAC0 Accumulator Byte 1 Register.......................................165
Figure 13.17. MAC0ACC0: MAC0 Accumulator Byte 0 Register.......................................165
Figure 13.18. MAC0OVR: MAC0 Accumulator Overflow Register....................................165
Figure 13.19. MAC0RNDH: MAC0 Rounding Register High Byte.....................................166
Figure 13.20. MAC0RNDL: MAC0 Rounding Register Low Byte......................................166
14. RESET SOURCES ..............................................................................................................167
Figure 14.1. Reset Sources ....................................................................................................167
Figure 14.2. Reset Timing .....................................................................................................168
Figure 14.3. WDTCN: Watchdog Timer Control Register ...................................................170
Figure 14.4. RSTSRC: Reset Source Register.......................................................................171
15. OSCILLATORS...................................................................................................................173
Figure 15.1. Oscillator Diagram ............................................................................................173
Figure 15.2. OSCICL: Internal Oscillator Calibration Register ............................................174
Figure 15.3. OSCICN: Internal Oscillator Control Register .................................................174
Figure 15.4. CLKSEL: System Clock Selection Register .....................................................175
Figure 15.5. OSCXCN: External Oscillator Control Register...............................................176
Figure 15.6. PLL Block Diagram ..........................................................................................178
Figure 15.7. PLL0CN: PLL Control Register........................................................................180
Figure 15.8. PLL0DIV: PLL Pre-divider Register ................................................................180
Figure 15.9. PLL0MUL: PLL Clock Scaler Register ............................................................181
Figure 15.10. PLL0FLT: PLL Filter Register........................................................................181
16. FLASH MEMORY ..............................................................................................................185
Figure 16.1. FLASH Memory Map for MOVC Read and MOVX Write Operations...........186
Figure 16.2. FLASH Program Memory Map and Security Bytes .........................................189
Figure 16.3. FLACL: FLASH Access Limit .........................................................................190
Figure 16.4. FLSCL: FLASH Memory Control ....................................................................191
Figure 16.5. PSCTL: Program Store Read/Write Control .....................................................192
17. BRANCH TARGET CACHE.............................................................................................193
Figure 17.1. Branch Target Cache Data Flow .......................................................................193
Figure 17.2. Branch Target Cache Organiztion .....................................................................194
Figure 17.3. Cache Lock Operation.......................................................................................195
Figure 17.4. CCH0CN: Cache Control Register....................................................................196
Figure 17.5. CCH0TN: Cache Tuning Register ....................................................................197
Figure 17.6. CCH0LC: Cache Lock Control Register...........................................................197
Figure 17.7. CCH0MA: Cache Miss Accumulator................................................................198
Figure 17.8. FLSTAT: FLASH Status...................................................................................198
18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................199
12 Rev. 1.2