Figure 22.10. Sbuf0: Uart0 Data Buffer Register; Figure 22.11. Saddr0: Uart0 Slave Address Register; Figure 22.12. Saden0: Uart0 Slave Address Enable Register - Silicon Laboratories C8051F120 Manual

Figure 22.10. SBUF0: UART0 Data Buffer Register

R/W R/W
Bit7 Bit6
Bits7-0: SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB)
This is actually two registers; a transmit and a receive buffer register. When data is moved to SBUF0,
it goes to the transmit buffer and is held for serial transmission. Moving a byte to SBUF0 is what ini-
tiates the transmission. When data is moved from SBUF0, it comes from the receive buffer.

Figure 22.11. SADDR0: UART0 Slave Address Register

R/W R/W
Bit7 Bit6
Bits7-0: SADDR0.[7:0]: UART0 Slave Address
The contents of this register are used to define the UART0 slave address. Register SADEN0 is a bit
mask to determine which bits of SADDR0 are checked against a received address: corresponding bits
set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0 are "don't cares".

Figure 22.12. SADEN0: UART0 Slave Address Enable Register

R/W R/W
Bit7 Bit6
Bits7-0: SADEN0.[7:0]: UART0 Slave Address Enable
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0 slave
address.
0: Corresponding bit in SADDR0 is a "don't care".
1: Corresponding bit in SADDR0 is checked against a received address.
R/W R/W R/W
Bit5 Bit4 Bit3
R/W R/W R/W
Bit5 Bit4 Bit3
R/W R/W R/W
Bit5 Bit4 Bit3
Rev. 1.2
C8051F120/1/2/3/4/5/6/7
R/W R/W
Bit2 Bit1
SFR Address:
R/W R/W
Bit2 Bit1
SFR Address:
R/W R/W
Bit2 Bit1
SFR Address:
R/W Reset Value
00000000
Bit0
0x99
SFR Page: 0
R/W Reset Value
00000000
Bit0
0xA9
SFR Page: 0
R/W Reset Value
00000000
Bit0
0xB9
SFR Page: 0
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