C8 051 F55x / 56x/ 57 x Notes: Use the Reset icon in the IDE to reset the target when connected during a debug session. Remove power from the target board and the USB Debug Adapter before connecting or disconnecting the ...
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C8 05 1 F 5 5x /5 6x / 57 x development. Choosing parts and families in this step affects the displayed or filtered parts in the later device selection menus. Choose the C8051F55x/56x/57x family by checking the C8051F55x/56x/57x check box. Modify part selection time...
C8 051 F55x / 56x/ 57 x 4.3. CP210x USB to UART VCP Driver Installation The Target Board includes a Silicon Labs CP210x USB-to-UART Bridge Controller. Device drivers for the CP210x need to be installed before the PC software can communicate with the MCU through the UART interface. 1.
C8 05 1 F 5 5x /5 6x / 57 x 5. Target Board The C8051F560 Development Kit includes a target board with a C8051F568 (Side A) and C8051F550 (Side B) device pre-installed for evaluation and preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping using the target board.
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C8 051 F55x / 56x/ 57 x Figure 4. C8051F560 Target Board with Pin Numbers Rev. 0.2...
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C8 05 1 F 5 5x /5 6x / 57 x 5.1. Target Board Shorting Blocks: Factory Defaults The C8051F560 Target Board comes from the factory with pre-installed shorting blocks on many headers. Figure 5 shows the positions of the factory default shorting blocks. Figure 5.
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C8 051 F55x / 56x/ 57 x 5.2. Target Board Power Options and Current Measurement (J4, J6, J7, J24, P4, TB1) The MCUs on the C8051F560 Target Board are powered from a +5 V net. The +5 V net is connected to the headers J4 and J24 (Side A) and J6 (Side B).
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C8 05 1 F 5 5x /5 6x / 57 x 5.4. Switches and LEDs (J15, J19) Two push-button switches are provided on the target board for each MCU. Switch RESET_A is connected to the RST pin of the C8051F568. Switch RESET_B is connected to the RST pin of the C8051F550. Pressing RESET_A puts the C8051F568 device into its hardware-reset state, and similarly for RESET_B and the C8051F550 MCU.
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C8 051 F55x / 56x/ 57 x 5.6. Serial Interface (P5, J17) A USB-to-UART bridge circuit (U5) and USB connector (P5) are provided on the target board to facilitate serial connections to UART0 of the C8051F568 (Side A). The Silicon Labs CP2102 USB-to-UART bridge provides data connectivity between the C8051F568 and the PC via a USB port.
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C8 05 1 F 5 5x /5 6x / 57 x 5.8. LIN Interface and Network (J12, J17, J21, TB1) Both MCUs on the target board are connected to LIN transceivers through headers. These headers assume that the MCU’s crossbars are configured to put the LIN TX and RX pins on port pins P1.0 and P1.1 respectively. See the C8051F55x/56x/57x data sheet for crossbar configuration.
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C8 051 F55x / 56x/ 57 x 5.9. Port I/O Connectors (J0-J3 and J11, J13, J16) Each of the parallel ports of the C8051F568 (Side A) and C8051F550 (Side B) has its own 10-pin header connector. Each connector provides a pin for the corresponding port pins 0-7, +5 V VIO, and digital ground. The same pin-out is used for all of the port connectors.
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C8 05 1 F 5 5x /5 6x / 57 x 5.11. Expansion Connector (P1) The 96-pin expansion I/O connector P1 is used to connect daughter boards to the main target board. P1 provides access to many C8051F568 signal pins. Pins for VREGIN, VDD, VIO, and 3.3V are also available. See Table 10 for a complete list of pins available at P1.
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C8 051 F55x / 56x/ 57 x external memory interface. The output pins of the latch are connected to the 96-pin header and include an _L suffix in the pin name. 5.12. Potentiometer (J20) The C8051F568 (Side A) device has the option to connect port pin P1.2 to a 10K linear potentiometer (R27). The potentiometer is connected through the J20 header.
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C8 05 1 F 5 5x /5 6x / 57 x 5.16. Target Board Pin Assignment Summary Some GPIO pins of the C8051F568 MCU can have an alternate fixed function. For example, pin 38 on the C8051F568 MCU is designated P0.4, and can be used as a GPIO pin. Also, if the UART0 peripheral on the MCU is enabled using the crossbar registers, the TX signal is routed to this pin.
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C8 051 F55x / 56x/ 57 x Table 12. C8051F560 Target Board Pin Assignments and Headers (Continued) MCU Pin Name Pin# Primary Alternate Fixed Target Board Relevant Headers Function Function Function P3.1 P3.1 GPIO J3[2] P3.2 P3.2 GPIO J3[3] P3.3 P3.3 GPIO J3[4]...
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C8 05 1 F 5 5x /5 6x / 57 x 6. Schematics Rev. 0.2...
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